Vertical thin-channel memory

Patent metadata

Field	Value
Publication number	US-9698156-B2
Application number	US-201514637187-A
Country	US
Kind code	B2
Filing date	Mar 3, 2015
Priority date	Mar 3, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A memory device which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films having outside surfaces and inside surfaces, the outside surfaces disposed on the data storage structures on the sidewalls of the corresponding even and odd stacks in the plurality of stacks forming a 3D array of memory cells, the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films.

First claim

The invention claimed is:

1. A memory device, comprising: first and second stacks of conductive strips having sidewalls;
data storage structures on the sidewalls of the conductive strips in the first and second stacks, and on top surfaces of the first and second stacks;
first and second vertical thin channel films having outside surfaces and inside surfaces, the outside surfaces disposed on the data storage structures on the sidewalls of the first and second stacks;
first memory cells at cross-points between the outside surfaces of the first vertical thin channel films and the conductive strips in the first stacks of conductive strips, and second memory cells at cross-points between the outside surfaces of the second vertical thin channel films and the conductive strips in the second stacks of conductive strips;
a reference conductor below the first and second stacks, and wherein the first and second vertical thin channel films are in physical contact with the reference conductor; and
insulating structures isolating the first vertical thin channel films of adjacent first memory cells along the conductive strips in the first stack of conductive strips, and isolating the second vertical thin channel films of adjacent second memory cells along the conductive strips in the second stack of conductive strips.

2. The memory device of claim 1 , including a solid dielectric material between the inside surfaces of the first and second vertical thin channel films.

3. The memory device of claim 1 , including a gap between the inside surfaces of the first and second vertical channel films.

4. The memory device of claim 1 , wherein the data storage structure comprises a multilayer dielectric charge trapping structure.

5. The memory device of claim 1 , including a conductive element connecting the first and second vertical thin channel films at upper ends, a bit line over the first and second stacks, and an interlayer connector connecting the bit line to the conductive element.

6. The memory device of claim 1 , wherein the vertical thin channel films have a width, and the data storage structures include dielectric charge storage layers having a width that is less than the width of the vertical thin channel films.

7. A memory device including a plurality of memory cells, comprising:
a plurality of stacks of conductive strips, the plurality including adjacent first and second stacks, the first stack having a first side and a second side and the second stack having a first side opposed to the second side of the first stack, and a second side;
data storage structures on sidewalls of the conductive strips on the first and second sides of the stacks, and on top surfaces of the first and second stacks;
a first thin-film semiconductor strip disposed vertically in contact with the data storage structure on the first side of the first stack;
a second thin-film semiconductor strip disposed vertically in contact with the data storage structures on the second side of the first stack;
a third thin-film semiconductor strip disposed vertically in contact with the data storage structure on the first side of the second stack;
a fourth thin-film semiconductor strip disposed vertically in contact with the data storage structures on the second side of the second stack;
the memory cells in the plurality of memory cells having channels in the thin-film semiconductor strips and gates in the conductive strips;
a patterned conductor layer or layers over the plurality of stacks;
a first interlayer connector connecting a first conductor in the patterned conductor layer or layers to a top surface of the first thin-film semiconductor strip;
a second interlayer connector connecting a second conductor in the patterned conductor layer or layers to a top surface of the second and third thin-film semiconductor strips;
a reference conductor below the plurality of stacks, and wherein the second thin-film semiconductor strip and the third thin-film semiconductor strip are physically connected to the reference conductor between the adjacent first and second stacks; and
a third interlayer connector connecting a third conductor in the patterned conductor layer or layers to a top surface of the fourth thin-film semiconductor strip.

8. The memory device of claim 7 , including a gap between the second and third thin-film semiconductor strips.

9. The memory device of claim 8 , including insulating layers on the second thin-film semiconductor strip and on the third thin-film semiconductor strip, the insulating layers being separated by said gap.

10. A memory device, comprising:
a plurality of stacks of conductive strips having sidewalls, the plurality of stacks including even stacks and odd stacks;
data storage structures on the sidewalls of the conductive strips in the plurality of stacks including the even and odd stacks, and on top surfaces of the plurality of stacks including the even and odd stacks;
a plurality of active pillars arranged between corresponding even and odd stacks of conductive strips in the plurality of stacks, active pillars in the plurality comprising even and odd vertical thin channel films having outside surfaces and inside surfaces, defining a multi-layer array of interface regions at cross-points between outside surfaces of the even and odd vertical thin channel films and conductive strips in the corresponding even and odd stacks of conductive strips;
a 3D array of even memory cells in the interface regions accessible via the active pillars and conductive strips in the even stacks of conductive strips and odd memory cells in the interface regions accessible via the active pillars and conductive strips in the odd stacks of conductive strips, wherein the odd memory cells on a given active pillar are configured as a first NAND string, and the even memory cells on said given active pillar are configured as a second NAND string, and wherein the inside surfaces of the even and odd vertical thin channel films of said given active pillar are separated in the interface regions;
insulating structures isolating the even vertical thin channel films of adjacent even memory cells along the conductive strips in the even stacks, and isolating the odd vertical thin channel films of adjacent odd memory cells along the conductive strips in the odd stacks;
conductive strips in an upper level in the even and odd stacks being configured as string select lines for both the first and second NAND strings on a given active pillar;
conductive strips in intermediate levels in the even and odd stacks being configured as word lines for respective ones of the first and second NAND strings on a given active pillar;
conductive strips in a lower level in the even and odd stacks being configured as ground select lines for both the first and second NAND strings on a given active pillar;
a reference conductor beneath and physically connected to active pillars in the plurality of active pillars; and
control circuitry configured to apply different bias voltages to the even and odd conductive strips.

11. The memory device of claim 10 , wherein active pillars in the plurality of active pillars include a dielectric material separating the even and odd vertical thin channel films.

12. The memory device of claim 10 , wherein active pillars in the plurality of active pillars include a gap separating the even and odd vertical thin channel films.

13. The memory device of claim 10 , wherein the plurality of stacks of conductive strips are arranged in blocks, and in a given block, conductive strips in a given layer of an odd stack are configured in a comb-like structure with strips extending from an odd pad, and co

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting

Classifications

• H01L29/66742

  Electricity · mapped topic

• H01L29/786

  Electricity · mapped topic

• H01L29/511

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic