U-shaped vertical thin-channel memory

Patent metadata

Field	Value
Publication number	US-9524980-B2
Application number	US-201514637204-A
Country	US
Kind code	B2
Filing date	Mar 3, 2015
Priority date	Mar 3, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

First claim

What is claimed is:

1. A memory device including a plurality of memory cells, comprising:
first and second stacks of conductive strips separated by a trench, the conductive strips in the first and second stacks having sidewalls on first and second sides, respectively, of the trench;
data storage structures on the sidewalls of the conductive strips;
a vertical channel structure having a first semiconductor film disposed vertically in contact with the data storage structures on the first side of the trench, and a second semiconductor film disposed vertically in contact with the data storage structures on the second side of the trench, and electrically connected between the first stack and the second stack to the first semiconductor film;
the memory cells in the plurality of memory cells having channels in the first and second semiconductor films and gates in the conductive strips in the first and second stacks; and
a patterned conductor layer or layers over the first stack and the second stack, a first interlayer connector connecting a first conductor in the patterned conductor layer or layers to a top surface of the first semiconductor film, and a second interlayer connector connecting a second conductor in the patterned conductor layer or layers to a top surface of the second semiconductor film;
wherein an upper strip in the first stack is configured as a gate of a first switch having a channel in the first semiconductor film, and an upper strip in the second stack is configured as a gate of a second switch having a channel in the second semiconductor film.

2. The memory device of claim 1 , including:
a plurality of vertical channel structures, including said first mentioned vertical channel structure, at least a second vertical channel structure in the plurality having a first semiconductor film disposed vertically in contact with data storage structures on the first side of the trench, and a second semiconductor film disposed vertically in contact with data storage structures on the second side of the trench, and electrically connected between the first stack and the second stack to the first semiconductor film; and
wherein a top surface of the second semiconductor film of said second vertical channel structure is electrically connected to the top surface of the second semiconductor film in the first mentioned vertical channel structure.

3. The memory device of claim 2 , including a third interlayer connector connecting a third conductor in the patterned conductor layer or layers to a top surface of the second semiconductor film in the second vertical channel structure.

4. The memory device of claim 2 , including:
a third stack of conductive strips disposed next to and separated by a second trench from the second stack, the conductive strips in the second and third stacks having sidewalls on first and second sides, respectively, of the second trench;
data storage structures on the sidewalls of the conductive strips in the second trench; and
the plurality of vertical channel structures including a third vertical channel structure having a first semiconductor film disposed vertically in contact with the data storage structures on the first side of the second trench, and a second semiconductor film disposed vertically in contact with the data storage structures on the second side of the second trench, and electrically connected between the second stack and the third stack to the first semiconductor film;
wherein a top surface of the first semiconductor film of said third vertical channel structure is electrically connected to the top surface of the second semiconductor film in the first mentioned vertical channel structure.

5. The memory device of claim 4 , including a third interlayer connector connecting a third conductor in the patterned conductor layer or layers to a top surface of the first semiconductor film in the second vertical channel structure.

6. The memory device of claim 1 , including an insulating structure separating the first and second semiconductor films in frustums of the vertical channel structure at which memory cells are disposed.

7. The memory device of claim 6 , wherein the insulating structure comprises a gap.

8. The memory device of claim 1 , including an insulating layer below the first stack and the second stack.

9. A memory device, comprising:
a plurality of stacks of conductive strips, the plurality of stacks including even stacks and odd stacks having sidewalls, at least some of the conductive strips in the stacks configured as word lines;
data storage structures on the sidewalls of the even and odd stacks; and
a plurality of active pillars between corresponding even and odd stacks of conductive strips in the plurality of stacks, active pillars in the plurality comprising semiconductor films having outside surfaces and inside surfaces, the outside surfaces disposed on the data storage structures on the sidewalls of the corresponding even and odd stacks in the plurality of stacks forming a 3D array of memory cells, and connected to form a current path from an upper end to a lower end of one of the semiconductor films having an outside surface disposed on the data storage structures on the sidewalls of one of the even stacks, and from a lower end to an upper end of another of the semiconductor films having an outside surface disposed on the data storage structures on the sidewalls of one of the odd stacks; and
wherein the even stacks of conductive strips include upper levels configured as string select lines, and the odd stacks of conductive strips include upper levels configured as ground select lines.

10. The memory device of claim 9 , wherein active pillars in the plurality of active pillars include a solid dielectric material separating the even and odd vertical channel films.

11. The memory device of claim 9 , wherein active pillars in the plurality of active pillars include a gap separating the even and odd vertical channel films.

12. The memory device of claim 9 , including control circuitry configured to apply different bias voltages to the conductive strips in the even and odd stacks.

13. The memory device of claim 9 , wherein the memory cells along the vertical channel films have channel thicknesses less than 10 nanometers.

14. The memory device of claim 9 , wherein the data storage structures comprise multilayer dielectric charge trapping structures.

15. The memory device of claim 14 , including one or more patterned conductor layers over the plurality of stacks, including bit lines, and interlayer connectors connecting the bit lines to corresponding active pillars.

16. The memory device of claim 9 , wherein at least one of the even stacks and odd stacks of conductive strips include lower levels configured as assist gates.

17. The memory device of claim 9 , including one or more patterned conductor layers over the plurality of stacks, including bit lines and at least one source line, and interlayer connectors connecting the bit lines to corresponding even vertical channel films and connecting the at least one source line to corresponding odd vertical channel films.

18. The memory device of claim 9 , wherein the plurality of stacks of conductive strips are arranged in blocks, and in a given block, conductive strips in a given layer of an odd stack are configured in a comb-like structure with strips extending from an odd pad, and conductive strips in the given layer of an even stack are configured in a comb-like structure with strips extending from an even pad, the conductive strips extending from the odd and eve

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title