Thick-silver layer interface for a semiconductor die and corresponding thermal layer

Patent metadata

Field	Value
Publication number	US-9698116-B2
Application number	US-201414530285-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.

First claim

We claim:

1. A semiconductor device comprising:
a die including at least one of a gallium nitride (GaN) layer, a gallium arsenide (GaAs) layer, and a silicon (Si) substrate;
a planar thermal layer including a copper thermal layer;
a thick-silver layer comprising a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer; and
a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer and coupling the die to the thick-silver layer, wherein the metallurgical die-attach includes a silver sinter die-attach.

2. The semiconductor device of claim 1 , wherein the planar thermal layer has a coefficient of thermal expansion (CTE) that is more than a CTE of the die.

3. The semiconductor device of claim 2 , wherein the planar thermal layer has a CTE that is at least two-and-a-half times the CTE of the die.

4. The semiconductor device of claim 1 , wherein the thick-silver layer is formed onto the first planar side of the planar thermal layer by electro-plating.

5. The semiconductor device of claim 1 , including a barrier layer including copper (Cu), nickel (Ni), nickel/gold (Ni/Au), tin (Sn), nickel/tin (Ni/Sn), or nickel/palladium/gold (Ni/Pd/Au), the barrier layer disposed onto a second planar side of the planar thermal layer.

6. The semiconductor device of claim 1 , including gold (Au) or silver (Ag) disposed onto an underside of the die.

7. A semiconductor device comprising:
a die including a gallium nitride (GaN) layer and a substrate including silicon (Si), silicon carbide (SiC), or diamond;
a copper planar thermal layer including at least one of Cu-151 and Cu-102;
a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the copper planar thermal layer; and
a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer and coupling the die to the thick-silver layer, wherein the metallurgical die-attach includes a silver sinter die-attach or a gold-tin (AuSn) die-attach.

8. The semiconductor device of claim 7 , including:
a barrier layer disposed onto a second planar side of the copper planar thermal layer, the barrier layer including copper (Cu), nickel (Ni), nickel/gold (Ni/Au), tin (Sn), nickel/tin (Ni/Sn), or nickel/palladium/gold (Ni/Pd/Au).

Assignees

• Viswanathan Lakshminarayan
• Molla Jaynal A
• Nxp Usa Inc

Inventors

• Viswanathan Lakshminarayan
• Molla Jaynal A

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07337

  using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title