Arrangement having a plurality of chips and a chip carrier, and a processing arrangement

Patent metadata

Field	Value
Publication number	US-9698070-B2
Application number	US-201313860679-A
Country	US
Kind code	B2
Filing date	Apr 11, 2013
Priority date	Apr 11, 2013
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

First claim

What is claimed is:

1. An arrangement, comprising:
a plurality of chips;
a chip carrier carrying the plurality of chips,
the chip carrier comprising a chip carrier notch extending from a lateral perimeter of the chip carrier into the chip carrier; and
an encapsulation material encapsulating the chip carrier and
filling the chip carrier notch;
wherein an outer circumference of the encapsulation material is free from a recess.

2. The arrangement of claim 1 ,
wherein the outer circumference of the encapsulation material is free from an alignment mark recess.

3. The arrangement of claim 1 ,
wherein the chip carrier is a wafer;
wherein the plurality of chips is monolithically integrated in the wafer.

4. The arrangement of claim 1 ,
wherein the chip carrier is an embedded encapsulation chip carrier.

5. The arrangement of claim 1 ,
wherein the chip carrier is a printed circuit board.

6. The arrangement of claim 1 ,
wherein the chip carrier is an interposer structure.

7. The arrangement of claim 1 ,
wherein the chip carrier has a polygonal shape.

8. The arrangement of claim 1 ,
wherein the encapsulation material at least partially covers a first main side and at least one sidewall of the chip carrier.

9. The arrangement of claim 8 ,
wherein the encapsulation material at least partially covers a second main side of the chip carrier being opposite the first main side of the chip carrier.

10. The arrangement of claim 1 ,
wherein a lateral extension of the encapsulation material is larger than a lateral extension of the chip carrier.

11. A processing arrangement, comprising:
a carrier configured to carry a chip carrier;
an arrangement, comprising:
a plurality of chips;
the chip carrier carrying the plurality of chips, the chip carrier comprising a chip carrier notch extending from a lateral perimeter of the chip carrier into the chip carrier;
an encapsulation material encapsulating the chip carrier and filling the chip carrier notch,
wherein an outer circumference of the encapsulation material is free from a recess;

a chip carrier notch position detector configured to detect a position of the chip carrier notch.

12. The processing arrangement of claim 11 ,
wherein the chip carrier notch position detector is configured to detect the position of the chip carrier notch based on light reflected by the chip carrier.

13. The processing arrangement of claim 11 ,
wherein the chip carrier notch position detector comprises at least one camera.

14. The processing arrangement of claim 11 ,
wherein the chip carrier notch position detector comprises a two-dimensional imaging array.

15. An arrangement, comprising:
a plurality of chips;
a chip carrier carrying the plurality of chips, the chip carrier comprising a chip carrier notch; and
an encapsulation material encapsulating the chip carrier and filling the chip carrier notch, wherein a lateral extension of the encapsulation material is larger than a lateral extension of the chip carrier;
wherein an outer circumference of the encapsulation material is free from a recess.

Assignees

• Infineon Technologies Ag

Inventors

• Ledutke Michael
• Fuergut Edward

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

• H10P72/165

  characterised by a material, a roughness, a coating or the like · CPC title

• H10W74/114 Primary

  by a substrate and the encapsulations · CPC title

• H10W74/014

  using batch processing · CPC title