Printed circuit board with thermal via

Patent metadata

Field	Value
Publication number	US-9693445-B2
Application number	US-201514611121-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A PCB includes a copper seed layer, a dielectric layer provided on the copper seed layer, a first thermal via and a plurality of second thermal vias disposed around the first thermal via. The first thermal via has a first through-hole in the dielectric layer and a first copper portion filled in the first through-hole, and each of the second thermal vias has a second through-hole in the dielectric layer and a second copper portion filled in the second through-hole. A mounting portion configured to mount a semiconductor device thereon is provided on the first copper portion.

First claim

What is claimed is:

1. A printed circuit board (PCB), comprising:
a copper seed layer;
at least one dielectric layer provided on the copper seed layer;
a single primary thermal via having a single first through-hole in the at least one dielectric layer ending at the copper seed layer, and a first copper portion filled in the first through-hole and directly contacting the copper seed layer, thereby enabling a direct electrical and thermal connection between the copper seed layer and the single primary thermal via;
a plurality of secondary thermal vias disposed peripherally around the single primary thermal via, each of the secondary thermal vias having a second through-hole in the at least one dielectric layer and a second copper portion filled in the second through-hole, the second copper portion directly contacting the copper seed layer at one end, thereby enabling a direct electrical and thermal connection between each of the plurality of secondary thermal vias and the copper seed layer allowing for each of the plurality of secondary thermal vias to be electrically and thermally connected to the single primary thermal via and other secondary thermal vias of the plurality of secondary thermal vias; and
a mounting portion provided within a surface area of the first copper portion for mounting a semiconductor device thereon,
wherein an exposed area of the single primary thermal via is larger than an exposed area of each of the secondary thermal vias.

2. The PCB of claim 1 , wherein the mounting portion is provided only on the first copper portion.

3. The PCB of claim 1 , wherein a shape of the first through-hole on a surface of the PCB is rectangular, as viewed in a direction perpendicular to the surface of the PCB.

4. The PCB of claim 1 , wherein a deposition height of the first copper portion is shorter than a depth of the first through-hole.

5. The PCB of claim 1 , wherein each of the secondary thermal vias is disposed at a regular interval around the single primary thermal via on a surface of the PCB, as viewed in a direction perpendicular to the surface of the PCB.

6. The PCB of claim 1 , wherein a diameter of the second through-hole on a surface of the PCB is 120 μm or less, as viewed in a direction perpendicular to the surface of the PCB.

7. The PCB of claim 1 , wherein the first through-hole extends from a surface of the PCB to the copper seed layer and penetrates through the at least one dielectric layer.

8. The PCB of claim 1 , wherein the single primary thermal via includes a single primary thermal via pad disposed along a periphery of the single first through-hole on a surface of the PCB, an exposed surface of the first copper portion and a surface of the single primary thermal via pad are substantially coplanar, and
each of the secondary thermal vias includes a secondary thermal via pad disposed along a periphery of the second through-hole on the surface of the PCB, an exposed surface of each of the second copper portion and a surface of the secondary thermal via pad are substantially coplanar.

9. The PCB of claim 1 , wherein a first end of each second copper portion is substantially co-planar with a surface of a secondary thermal via pad disposed along a periphery of the second through-hole on a surface of the PCB, and a second end of each second copper portion corresponds to the one end of the second copper portion directly contacting the copper seed layer.

10. The PCB of claim 1 , wherein the plurality of secondary thermal vias are disposed peripherally around all sides of the single primary thermal via.

11. The PCB of claim 1 , wherein the at least one dielectric layer comprises an upper dielectric layer stacked on a lower dielectric layer; and
wherein the plurality of secondary thermal vias comprise a plurality of upper secondary thermal vias stacked on and in contact with a plurality of lower secondary thermal vias.

12. The PCB of claim 11 , wherein a diameter at a top of the upper secondary thermal via is substantially identical to a diameter at a top of the lower secondary thermal via as viewed in a direction perpendicular to a surface of the PCB.

13. The PCB of claim 11 , wherein the lower and upper secondary thermal vias are connected to the single primary thermal via by the copper seed layer.

14. A printed circuit board (PCB), comprising:
a plurality of dielectric layers;
an electrically and thermally conductive seed layer sandwiched between a pair of dielectric layers of the plurality of dielectric layers;
a single primary thermal via extending to the seed layer within the PCB through at least one of the plurality of dielectric layers, thereby enabling a direct electrical and thermal connection between the seed layer and the single primary thermal via, wherein the single primary thermal via is configured to receive a semiconductor die;
a plurality of secondary thermal vias disposed peripherally around the single primary thermal via to surround the single primary thermal via, the plurality of secondary thermal vias extending from a surface of the PCB to the seed layer through the at least one of the plurality of dielectric layers, thereby enabling a direct electrical and thermal connection between the seed layer and each of the plurality of secondary thermal vias allowing for each of the plurality of secondary thermal vias to be electrically and thermally connected to the single primary thermal via and other secondary thermal vias of the plurality of secondary thermal vias,
wherein an exposed area of the single primary thermal via on the surface of the PCB is larger than an exposed area of each of the secondary thermal vias on the surface of the PCB.

15. The PCB of claim 14 , further comprising:
a mounting portion provided within a surface area of the single primary thermal via for receiving the semiconductor die, wherein the mounting portion is provided only on the single primary thermal via.

16. The PCB of claim 14 , wherein the single primary thermal via has a through-hole and a copper portion filled in the through-hole, and a deposition height of the copper portion is shorter than a depth of the through-hole.

17. The PCB of claim 14 , wherein the secondary thermal vias are disposed at a regular interval peripherally around the single primary thermal via on the surface of the PCB, as viewed in the direction perpendicular to the surface of the PCB.

18. An apparatus, comprising:
a printed circuit board (PCB), the PCB comprising:
a copper seed layer;
at least one dielectric layer provided on the copper seed layer;
a single primary thermal via consisting of one first through-hole extending through the at least one dielectric layer of the PCB to the copper seed layer, and a first copper portion filling the one first through-hole, thereby enabling a direct electrical and thermal connection between the copper seed layer and the single primary thermal via;
a plurality of secondary thermal vias disposed around an entire periphery of the single primary thermal via, each of the secondary thermal vias having a second through-hole in the at least one dielectric layer and a second copper portion filled in the second through-hole and directly contacting the copper seed layer at one end of the second copper portion, wherein only the one end of each second copper portion is directly electrically connected to the copper seed layer, thereby enabling a direct electrical and thermal connection between each of the plurality of secondary thermal vias and the copper seed layer allowing for each of the plurality of secondary thermal vias to be

Assignees

• Avago Technologies General Ip

Inventors

• Ku Hyun Mo
• Jeong Jin
• Choi Deog Soon
• Chung Chris

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W70/635

  Through-vias · CPC title