Wiring substrate

Patent metadata

Field	Value
Publication number	US-9324929-B2
Application number	US-201514689444-A
Country	US
Kind code	B2
Filing date	Apr 17, 2015
Priority date	Apr 24, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A wiring substrate includes a heat sink, an insulation layer, first and second wiring layers, first and second through wirings, and first and second pads. The insulation layer is arranged on the heat sink with an adhesive layer located in between. The insulation layer includes first and second through holes. The first and second wiring layers are arranged on a surface of the insulation layer in contact with the adhesive layer. The first and second wiring layers are embedded in the adhesive layer. The first through wiring formed in the first through hole is connected to the first wiring layer and thermally coupled to the semiconductor device. The second through wiring formed in the first through hole is connected to the second wiring layer and electrically connected to the semiconductor device. The pads cover exposed surfaces of the through wirings.

First claim

The invention claimed is:

1. A wiring substrate on which one of a semiconductor device and a module including a semiconductor device is mounted, the wiring substrate comprising:
a heat dissipation plate;
an adhesive layer arranged over the heat dissipation plate, wherein the adhesive layer has a first surface that is in contact with a surface of the heat dissipation plate, and a second surface that is located at an opposite side of the first surface; and
a wiring portion arranged over the adhesive layer, wherein the wiring portion is in contact with the second surface of the adhesive layer; wherein
the wiring portion includes:
an insulation layer arranged on the heat dissipation plate with the adhesive layer located in between, wherein the insulation layer includes a first through hole and a second through hole that extend through the insulation layer in a thicknesswise direction;
a first wiring layer and a second wiring layer arranged on a surface of the insulation layer in contact with the adhesive layer, wherein the first wiring layer and the second wiring layer are embedded in the adhesive layer;
a first through wiring connected to the first wiring layer and thermally coupled to the semiconductor device, wherein the first through hole of the insulation layer is filled with the first through wiring;
a second through wiring connected to the second wiring layer and electrically connected to the semiconductor device, wherein the second through hole of the insulation layer is filled with the second through wiring;
a first pad that covers a surface of the first through wiring exposed from the insulation layer, the first pad being provided in the surface opposite to the surface of the first through wiring in contact with the first wiring layer; and
a second pad that covers a surface of the second through wiring exposed from the insulation layer, the second pad being provided in the surface opposite to the surface of the second through wiring in contact with the second wiring layer, wherein
the surface of the heat dissipation plate is separated from surfaces of the first wiring layer and the second wiring layer, and
the adhesive layer fills from the surface of the heat dissipation plate to the surfaces of the first wiring layer and the second wiring layer.

2. The wiring substrate according to claim 1 , wherein the first through wiring and the first wiring layer are configured not to be electrically connected to the semiconductor device.

3. The wiring substrate according to claim 1 , wherein the first wiring layer is larger than the first through wiring in a plan view.

4. The wiring substrate according to claim 1 , wherein the first through wiring is larger than one of the semiconductor and the module in a plan view.

5. The wiring substrate according to claim 1 , wherein
the first through wiring is one of a plurality of first through wirings,
the first pad is one of a plurality of first pads,
the first through wirings are connected to the same first wiring layer,
each of the first pads is thermally coupled to the semiconductor device via a first bump,
the second through wiring is one of a plurality of second through wirings,
the second pad is one of a plurality of second pads,
the second through wirings are connected to the same second wiring layer, and
each of the second pads is electrically connected to the semiconductor device via a second bump.

6. The wiring substrate according to claim 1 , wherein the adhesive layer includes:
a first adhesive layer that bonds the first wiring layer and the second wiring layer to the insulation layer; and
a second adhesive layer that bonds the first adhesive layer, the first wiring layer, and the second wiring layer to the heat dissipation plate.

7. The wiring substrate according to claim 1 , comprising a protection layer arranged on the insulation layer, wherein the protection layer includes:
a first opening that exposes the first pad; and
a second opening that exposes the second pad.

8. The wiring substrate according to claim 7 , wherein
the semiconductor device includes a light emitting device, and
the protection layer includes a reflection film.

9. The wiring substrate according to claim 1 , wherein the first wiring layer and the first through wiring are electrically connected to the semiconductor device.

Assignees

• Shinko Electric Ind Co
• Shinko Electric Ind Co

Inventors

• Horikawa Yasuyoshi
• Denda Tatsuaki

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H05K1/18

  structurally associated with non-printed electric components (H05K1/16 takes precedence) · CPC title

• H05K1/0207

  using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes · CPC title

• H05K1/0206

  by printed thermal vias · CPC title