Wiring substrate and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9059152-B2
Application number	US-201213659147-A
Country	US
Kind code	B2
Filing date	Oct 24, 2012
Priority date	Oct 25, 2011
Publication date	Jun 16, 2015
Grant date	Jun 16, 2015

Abstract

Embodiments of the present invention provide a wiring substrate having a structure where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface. At least one among a plurality of the projection electrodes is a variant projection electrode which has a recess portion on an upper surface, an outer diameter at the upper end that is larger than an outer diameter at the lower end, and a reverse trapezoidal cross-section shape. Embodiments of the present invention also provide methods for manufacturing wiring substrates having one or more of said variant projection electrode.

First claim

What is claimed is:

1. A wiring substrate, comprising:
a multilayer portion that includes a plurality of interlayer insulation layers, each of the plurality of interlayer insulation layer including via holes having a reverse cone shape and via conductors formed in the via holes, a top-most interlayer insulation layer constituting a substrate main surface; and
a plurality of projection electrodes arranged within an electrode formation region on the substrate main surface, each of the plurality of projection electrodes directly formed on a respective via conductor in the reverse truncated cone shaped via hole of the top-most interlayer insulation layer;
wherein at least one among the plurality of projection electrodes comprises a variant projection electrode having a recess portion on an upper surface, an outer diameter at an upper end that is larger than an outer diameter at a lower end, and a reverse trapezoidal cross-section shape and a curved portion formed at a boundary area between the upper surface of the variant projection electrode and a lateral surface of the variant projection electrode.

2. The wiring substrate according to claim 1 ,
wherein an entire inner surface of the recess portion has a curved surface shape and a deepest portion of the recess portion is positioned on a center axis of the variant projection electrode.

3. The wiring substrate according to claim 1 ,
wherein all of the plurality of projection electrodes which are present within the electrode formation region comprise variant projection electrodes.

4. The wiring substrate according to claim 1 ,
wherein the plurality of projection electrodes are arrayed in vertical and horizontal rows along a surface direction of the substrate main surface within the electrode formation region, and
wherein, among the plurality of projection electrodes, projection electrodes positioned at an outer periphery of the electrode formation region comprise variant projection electrodes.

5. The wiring substrate according to claim 1 ,
wherein the variant projection electrode is in a flip chip interconnection with a plurality of connecting terminals positioned at a bottom surface side of a component via a solder bump placed on the recess portion.

6. A method of manufacturing the wiring substrate according to claim 1 , comprising:
preparing a multilayer portion formed by layering a plurality of interlayer insulation layers;
forming a resist on a top-most interlayer insulation layer that forms a substrate main surface;
forming an opening on the resist which has a larger inner diameter at an upper end side of the opening than an inner diameter at a lower end side of the opening; and
forming a variant projection electrode, which has a recess portion on an upper surface, at the opening by plating the inner side of the opening.

7. The method of manufacturing the wiring substrate according to claim 6 , further comprising:
forming a curved portion at a boundary area between the upper surface of the variant projection electrode and a lateral surface of the variant projection electrode by etching the variant projection electrode after forming the variant projection electrode.

Assignees

• Ngk Spark Plug Co

Inventors

• Inoue Masahiro
• Sugimoto Atsuhiko

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title