Pad-less interconnect for electrical coreless substrate

Patent metadata

Field	Value
Publication number	US-9691727-B2
Application number	US-201514686210-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Jun 24, 2008
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

First claim

What is claimed is:

1. An apparatus comprising:
a laminated mounting substrate including a die side and a land side;
a surface finish film disposed in a recess on the mounting substrate die side;
an electrically conductive first plug in contact with the surface finish film;
an electrically conductive subsequent plug disposed on the mounting substrate land side, electrically coupled to the electrically conductive first plug, and disposed directly below the electrically conductive first plug; and
a microelectronic die disposed above the laminated mounting substrate, wherein the microelectronic die is coupled to the laminated mounting substrate through an electrical contact that contacts the surface finish film;
wherein standoff between the laminated mounting substrate die side and the microelectronic die is 60 μm, wherein the electrical contact that contacts the surface finish layer has a diameter of 74 μm, and wherein pitch between the electrical contact in the recess and an adjacent electrical contact in an adjacent recess is 150 μm.

2. The apparatus of claim 1 , further including a board electrically coupled to the laminated mounting substrate at the land side.

3. The apparatus of claim 1 , wherein the surface finish film comprises a plurality of the layers.

4. The apparatus of claim 1 , wherein the surface finish film is planar to the laminated mounting substrate die side.

5. The apparatus of claim 1 , wherein the laminated mounting substrate comprises a plurality of dielectric layers.

6. The apparatus of claim 1 , further including an electrically conductive second plug disposed between the electrically conductive first plug and the electrically conductive subsequent plug.

7. The apparatus of claim 1 , wherein the electrical contact comprises a solder interconnect.

8. The apparatus of claim 1 , wherein the surface finish film includes a surface finish first film in physical contact with the electrically conductive first plug, and a surface finish second film disposed upon the surface finish first film, and wherein the surface finish first film is electrochemically more noble than the surface finish second film.

9. A computing system comprising:
a laminated mounting substrate including a die side and a land side;
a surface finish film disposed in a recess on the mounting substrate die side;
an electrically conductive first plug in contact with the surface finish film;
an electrically conductive subsequent plug disposed on the mounting substrate land side, electrically coupled to the electrically conductive first plug, and disposed directly below the electrically conductive first plug;
a microelectronic die disposed above the laminated mounting substrate, wherein the microelectronic die is coupled to the laminated mounting substrate through an electrical contact that contacts the surface finish film;
wherein standoff between the laminated mounting substrate die side and the microelectronic die is 60 μm, wherein the electrical contact that contacts the surface finish layer has a diameter of 74 μm, and wherein pitch between the electrical contact in the recess and an adjacent electrical contact in an adjacent recess is 150 μm;
a board electrically coupled to the laminated mounting substrate at the land side; and
an external memory coupled to the microelectronic die.

10. The apparatus of claim 1 , further including:
a board electrically coupled to the laminated mounting substrate at the land side, and wherein the board is electrically coupled through an electrical contact that has a diameter of 200 μm and a pitch of 400 μm.

11. An apparatus comprising:
a laminated mounting substrate including a die side and a land side;
a plurality of surface finish films, wherein each of the plurality of surface finish films is disposed in a respective recess of a plurality of recesses on the mounting substrate die side;
a plurality of electrically conductive first plugs in contact with respective surface finish films;
a plurality of electrically conductive subsequent plugs disposed on the mounting substrate land side, each electrically coupled to respective electrically conductive first plugs of the plurality of electrically conductive first plugs, wherein each of the plurality of electrically conductive plugs is disposed directly below its respective electrically conductive first plug; and
a microelectronic die disposed above the laminated mounting substrate, wherein the microelectronic die is coupled to the laminated mounting substrate through a plurality of electrical contacts that contacts respective surface finish films, wherein the plurality of electrical contacts includes at least one perimeter contact next to an edge of the laminated mounting substrate and at least one center contact, and wherein the at least one perimeter contact is larger than the at least one center contact;
wherein standoff between the laminated mounting substrate die side and the microelectronic die is 60 μm, wherein the electrical contact that contacts the surface finish layer has a diameter of 74 μm, and wherein pitch between the electrical contact in the recess and an adjacent electrical contact in an adjacent recess is 150 μm.

12. The apparatus of claim 11 , further including a board electrically coupled to the laminated mounting substrate at the land side.

13. The apparatus of claim 11 , wherein the surface finish film comprises a plurality of the layers.

14. The apparatus of claim 11 , wherein the surface finish film is planar to the laminated mounting substrate die side.

15. The apparatus of claim 11 , wherein the laminated mounting substrate comprises a plurality of dielectric layers.

16. The apparatus of claim 11 , further including an electrically conductive second plug disposed between the electrically conductive first plug and the electrically conductive subsequent plug.

17. The apparatus of claim 11 , wherein the electrical contact comprises a solder interconnect.

18. The apparatus of claim 11 , wherein the surface finish film includes a surface finish first film in physical contact with the electrically conductive first plug, and a surface finish second film disposed upon the surface finish first film, and wherein the surface finish first film is electrochemically more noble than the surface finish second film.

19. The computing system of claim 9 , wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.

Assignees

• Intel Corp

Inventors

• Soto Gonzalez Javier
• Gurumurthy Charavana K
• Nickerson Robert M
• Mallik Debendra

Classifications

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K3/20

  by affixing prefabricated conductor pattern {(H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence)} · CPC title

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K3/28

  Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} · CPC title

• H05K2201/0367

  Metallic bump or raised conductor not used as solder bump · CPC title