Enabling package-on-package (PoP) pad surface finishes on bumpless build-up layer (BBUL) package

Patent metadata

Field	Value
Publication number	US-9299602-B2
Application number	US-201113997146-A
Country	US
Kind code	B2
Filing date	Dec 20, 2011
Priority date	Dec 20, 2011
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit (IC) package, the method comprising:
providing a package core with a plurality of package-on-package (PoP) pad locations formed on the package core, wherein the plurality of PoP pad locations are plated with an etch layer of conductive material;
plating a sub-surface finish being a group-10 element onto the etch layer at the PoP pad locations;
forming at least one build-up layer including interconnects formed therein over a die disposed on the package core and the PoP pad locations; and
exposing the PoP pad locations on a side opposing the build-up layer.

2. The method of claim 1 , wherein the sub-surface finish is Pd to form a Pd PoP pad surface finish.

3. The method of claim 1 , wherein the sub-surface finish is Pd, and the method further comprises:
plating Ni onto the sub-surface finish to form a Ni—Pd PoP pad surface finish.

4. The method of claim 1 , wherein the sub-surface finish is Ni, and the method further comprises:
subsequent to exposing the PoP pad locations:
immersion plating gold (Au) onto the PoP pad locations to form a Ni—Au PoP pad surface finish.

5. The method of claim 1 , wherein the sub-surface finish is Ni, and the method further comprises:
subsequent to exposing the PoP pad locations:
electroless plating a Pd layer onto the PoP pad locations; and
immersion plating gold (Au) onto the Pd layer to form a Ni—Pd—Au PoP pad surface finish.

6. The method of claim 1 , wherein the sub-surface finish is Ni, and the method further comprises:
plating a layer of Pd onto the sub-surface finish;
subsequent to exposing the PoP pad locations:
electroless plating an additional Pd layer onto the PoP pad locations; and
immersion plating gold (Au) onto the additional Pd layer to form a Pd—Ni—Pd—Au PoP pad surface finish.

7. The method of claim 1 , wherein the step of providing the package core with the plurality of package-on-package (PoP) pad locations comprises:
providing a package core;
laminating an adhesive film onto a surface of the package core;
laminating a conductive foil of the conductive material onto the adhesive film;
laminating a patterned film layer to form the PoP pad locations; and
plating the etch layer onto the PoP pad locations.

8. The method of claim 1 , wherein the step of forming at least one build-up layer including interconnects comprises:
plating a conductive layer of the conductive material onto the PoP pad locations;
stripping the patterned film layer;
etching a portion of the conductive foil to expose an area of the adhesive film;
mounting the die onto the adhesive film;
forming one of the build-up layers over the die, comprising:
laminating a build-up film;
laser etching via locations;
plating a conductive interconnect layer connecting the via locations;

coating the conductive interconnect layer with a solder resist coating;
patterning the solder resist to form contact pad locations; and
coating the contact pad locations with a preservative.

9. The method of claim 8 , wherein the step of forming at least one build-up layer including interconnects further comprises:
forming additional build-up layers, wherein each additional build-up layer is formed by:
laminating an additional build-up film;
laser etching additional via locations through the additional build-up film;
plating an additional conductive interconnect layer connecting the additional via locations.

10. The method of claim 1 , wherein the step of exposing the PoP pad locations comprises:
separating the package core;
removing the adhesive film; and
etching away the etch layer and a remaining portion of the conductive foil.

11. The method of claim 1 , wherein the conductive material is copper (Cu).

12. The method of claim 7 , wherein the adhesive film is a polyethylene terephthalate (PET) film.

13. The method of claim 8 , wherein the build-up film is an Ajinomoto build-up film (ABF).

14. The method of claim 8 , wherein the preservative is an organic solderability preservative (OSP).

15. An integrated circuit package, comprising:
a die;
a bumpless build-up layer including a plurality of interconnect layers formed on an active side of the die; and
a plurality of package-on-package (PoP) pads formed on a first side of the bumpless build-up layer, wherein the PoP pads have a surface finish selected from a group consisting of Pd and Pd—Ni—Pd—Au.

16. The integrated circuit package of claim 15 , wherein the surface finish has a thickness being less than or equal to 300 nanometers (nm).

17. The integrated circuit package of claim 15 , wherein the surface finish has a thickness being less than or equal to 60 nm.

18. The integrated circuit package of claim 15 , further comprising a plurality of contact pad locations formed on a second side of the bumpless build-up layer opposing the first side.

19. The integrated circuit package of claim 15 , wherein an integrated circuit component is coupled to the PoP pads through a solder material to electrically connect the integrated circuit component to the die.

20. An integrated circuit package, comprising:
a die;
a bumpless build-up layer including a plurality of interconnect layers formed on an active side of the die; and
a plurality of package-on-package (PoP) pads having an amorphous pad surface finish formed on a first side of the bumpless build-up layer.

21. The integrated circuit package of claim 20 , wherein the amorphous pad surface finish is selected from a group consisting of Pd, Ni—Pd, Ni—Au, Ni—Pd—Au, and Pd—Ni—Pd—Au.

22. The integrated circuit package of claim 20 , wherein the amorphous pad surface finish comprises a phosphorus additive.

23. The integrated circuit package of claim 20 , wherein the amorphous pad surface finish has a thickness being less than or equal to 60 nm.

24. The integrated circuit package of claim 20 , further comprising a plurality of contact pads on a second side of the bumpless build-up layer opposing the first side.

25. The integrated circuit package of claim 20 , further comprising an electrical component coupled to the PoP pads through a solder material to electrically connect the electrical component to the die.

Assignees

• Zhang Qinglei
• Wu Tao
• Hlad Mark S
• Gurumurthy Charavana K
• Intel Corp

Inventors

• Zhang Qinglei
• Wu Tao
• Hlad Mark S
• Gurumurthy Charavana K

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/00 Primary

  Package configurations · CPC title