Coated round wire
US-2024368794-A1 · Nov 7, 2024 · US
US9691425B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9691425-B2 |
| Application number | US-201313969786-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 19, 2013 |
| Priority date | Feb 6, 2013 |
| Publication date | Jun 27, 2017 |
| Grant date | Jun 27, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
Opening claim text (preview).
What is claimed is: 1. A method of fabricating an on-chip lamination structure, the method comprising: depositing a seed layer on a substrate; patterning a photoresist layer to form an opening to the seed layer; forming the on-chip lamination structure within the opening, the on-chip lamination structure consisting of a magnetic unit layer consisting of first and second magnetic layers and a conductive non-magnetic spacer layer therebetween; and a resistive spacer disposed on the magnetic unit layer, wherein each respective layer is stackedly arranged, wherein the resistive spacer is a resistive material selected from the group consisting of selenium, bismuth, tellurium, phosphorous, sulfur, germanium, antimony, and alloys thereof that can be electrochemically reduced, wherein the resistive spacer is thicker and more resistive than the conductive non-magnetic spacer layer in the magnetic unit layer, wherein the conductive non-magnetic spacer layer is at a thickness of less than 300 Angstroms, and wherein the resistive spacer is at a thickness of 100 nanometers to 1 micron, wherein forming the on-chip lamination structure comprises electroplating the first and second magnetic layers, the conductive non-magnetic layer, and the resistive spacer; and removing the photoresist layer and a portion of the seed layer surrounding the on-chip lamination structure.
Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer · CPC title
Magnets · CPC title
via a non-magnetic spacer · CPC title
containing more than 50% by weight of copper · CPC title
the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.