Laminating magnetic cores for on-chip magnetic devices

US9691425B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9691425-B2
Application numberUS-201313969786-A
CountryUS
Kind codeB2
Filing dateAug 19, 2013
Priority dateFeb 6, 2013
Publication dateJun 27, 2017
Grant dateJun 27, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating an on-chip lamination structure, the method comprising: depositing a seed layer on a substrate; patterning a photoresist layer to form an opening to the seed layer; forming the on-chip lamination structure within the opening, the on-chip lamination structure consisting of a magnetic unit layer consisting of first and second magnetic layers and a conductive non-magnetic spacer layer therebetween; and a resistive spacer disposed on the magnetic unit layer, wherein each respective layer is stackedly arranged, wherein the resistive spacer is a resistive material selected from the group consisting of selenium, bismuth, tellurium, phosphorous, sulfur, germanium, antimony, and alloys thereof that can be electrochemically reduced, wherein the resistive spacer is thicker and more resistive than the conductive non-magnetic spacer layer in the magnetic unit layer, wherein the conductive non-magnetic spacer layer is at a thickness of less than 300 Angstroms, and wherein the resistive spacer is at a thickness of 100 nanometers to 1 micron, wherein forming the on-chip lamination structure comprises electroplating the first and second magnetic layers, the conductive non-magnetic layer, and the resistive spacer; and removing the photoresist layer and a portion of the seed layer surrounding the on-chip lamination structure.

Assignees

Inventors

Classifications

  • Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer · CPC title

  • Magnets · CPC title

  • via a non-magnetic spacer · CPC title

  • containing more than 50% by weight of copper · CPC title

  • the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

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What does patent US9691425B2 cover?
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification C25D5/10. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Jun 27 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).