Patterning methods, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated thereby

US9685606B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9685606-B2
Application numberUS-201514970163-A
CountryUS
Kind codeB2
Filing dateDec 15, 2015
Priority dateJan 23, 2015
Publication dateJun 20, 2017
Grant dateJun 20, 2017

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  5. First independent claim

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Abstract

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A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming patterns, comprising: forming an etch-target layer on a substrate; forming mask patterns on the etch-target layer; and etching the etch-target layer using the mask patterns as an etch mask to form patterns that are spaced apart from each other, wherein etching the etch-target layer comprises irradiating the etch-target layer with an ion beam, the ion beam having an incident energy in a range from 600 eV to 10 keV; wherein etching the etch-target layer comprises forming a recess region in the etch-target layer between the mask patterns; and wherein the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region, wherein the first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°. 2. The method of claim 1 , wherein an etch rate of the inner side surface of the recess region is greater than 60% of an etch rate of the bottom surface of the recess region. 3. The method of claim 1 , wherein the etch-target layer comprises a metallic element. 4. The method of claim 1 , wherein the incident energy is greater than 1 keV. 5. The method of claim 1 , wherein the incident energy is greater than 2 keV. 6. The method of claim 1 , wherein the incident energy is greater than 5 keV. 7. The method of claim 1 , wherein the inner side surface of the recess region is inclined at a third angle with respect to the top surface of the substrate, and wherein the second angle is expressed by θ 2 =180°−θ 1 −θ 3 , where θ 1 , θ 2 , and θ 3 denote the first, second, and third angles, respectively. 8. The method of claim 1 , wherein the recess region has a width that increases in the direction away from the top surface of the substrate. 9. The method of claim 1 , wherein the ion beam comprises positive ions of argon (Ar). 10. A method of fabricating a semiconductor device, comprising: forming a magnetic tunnel junction layer on a substrate; forming mask patterns on the magnetic tunnel junction layer; and etching the magnetic tunnel junction layer using the mask patterns as an etch mask to form magnetic tunnel junction patterns spaced apart from each other, wherein the etching process of the magnetic tunnel junction layer comprises irradiating the magnetic tunnel junction layer with an ion beam having an incident energy in a range from 600 eV to 10 keV; wherein etching the magnetic tunnel junction layer comprises forming a recess region in the magnetic tunnel junction between the mask patterns; and wherein the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region, wherein the first angle is greater than the second angle. 11. The method of claim 10 , wherein the magnetic tunnel junction layer comprises a first magnetic layer and a second magnetic layer, which are stacked on the substrate, and a tunnel barrier layer interposed between the first and second magnetic layers. 12. The method of claim 10 , wherein an etch rate of the inner side surface of the recess region is greater than 60% of an etch rate of the bottom surface of the recess region. 13. The method of claim 10 , wherein the inner side surface of the recess region is inclined at a third angle with respect to a top surface of the substrate, and the second angle is expressed by θ 2 =180°−θ 1 −θ 3 , where θ 1 , θ 2 , and θ 3 denote the first, second, and third angles, respectively. 14. The method of claim 10 , wherein the ion beam comprises positive ions of argon (Ar). 15. The method of claim 10 , wherein each of the magnetic tunnel junction patterns comprises a first magnetic pattern and a second magnetic pattern, which are stacked on the substrate, and a tunnel barrier pattern interposed between the first and second magnetic patterns, and each of the first and second magnetic patterns has a magnetization direction perpendicular to an interface between the second magnetic pattern and the tunnel barrier pattern. 16. The method of claim 10 , wherein each of the magnetic tunnel junction patterns comprises a first magnetic pattern and a second magnetic pattern, which are stacked on the substrate, and a tunnel barrier pattern interposed between the first and second magnetic patterns, and each of the first and second magnetic patterns has a magnetization direction parallel to an interface between the second magnetic pattern and the tunnel barrier pattern. 17. A method of forming patterns, comprising: forming an etch-target layer on a substrate; forming mask patterns on the etch-target layer; and etching the etch-target layer using the mask patterns as an etch mask to form patterns that are spaced apart from each other, wherein etching the etch-target layer comprises irradiating the etch-target layer with an ion beam, the ion beam having an incident energy in a range from 600 eV to 10 keV; wherein etching the etch-target layer comprises forming a recess region in the etch-target layer between the mask patterns; and wherein the incident energy is controlled in such a way that a first etch rate of an inner side surface of the recess region is greater than 60% of a second etch rate of a bottom surface of the recess region. 18. The method of claim 17 , wherein a first incidence angle of the ion beam with respect to the inner side surface of the recess region and a second incidence angle of the ion beam with respect to the bottom surface of the recess region are controlled in such a way that the first etch rate is greater than 60% of the second etch rate. 19. The method of claim 17 , wherein the first incidence angle ranges from 0° to 40° and the second incidence angle ranges from 50° to 90°.

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What does patent US9685606B2 cover?
A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 k…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P50/262. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 20 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).