Device performing refresh operations of memory areas

Patent metadata

Field	Value
Publication number	US-8958259-B2
Application number	US-201213444032-A
Country	US
Kind code	B2
Filing date	Apr 11, 2012
Priority date	Apr 13, 2011
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.

First claim

The invention claimed is:

1. A device comprising:
a plurality of memory areas operating independently of one another;
a plurality of control circuits respectively controlling self-refresh operations of the memory areas independently and asynchronously;
an oscillator outputting an oscillator signal having a first period; and
a refresh start signal generation circuit generating a plurality of refresh start signals having a second period longer than the first period based on the oscillator signal, the refresh start signals having activation timings different from one another,
wherein one of the memory areas corresponding to one of the control circuits that externally receives a self-refresh request is refreshed in response to an activation timing of a corresponding one of the refresh start signals.

2. The device according to claim 1 ,
wherein the control circuits further controls auto-refresh operations of the memory areas independently and asynchronously.

3. The device according to claim 1 , further comprising a plurality of command decoders respectively decoding externally input self-refresh commands to instruct self-refresh operations of the memory areas, the command decoders each controlling a corresponding one of the memory areas.

4. The device according to claim 3 , further comprising a plurality of command terminals receiving the self refresh commands, the command terminals corresponding to the memory areas respectively.

5. The device according to claim 4 , further comprising a plurality of data terminals inputting/outputting data of the memory areas from/to outside independently of and asynchronously with one another, the data terminals corresponding to the memory areas respectively.

6. The device according to claim 2 , further comprising a plurality of command decoders respectively decoding externally input self-refresh commands to instruct self-refresh operations of the memory areas and externally input auto-refresh commands to instruct auto-refresh operations of the memory areas, the command decoders each controlling a corresponding one of the memory areas.

7. The device according to claim 6 , further comprising a plurality of data terminals inputting/outputting data of the memory areas from/to outside independently of and asynchronously with one another, the data terminals corresponding to the memory areas respectively.

8. The device according to claim 7 , further comprising a plurality of command decoders respectively decoding externally input read commands and write commands to instruct operations associated with the inputting/outputting, the command decoders each controlling a corresponding one of the memory areas.

9. The device according to claim 8 , further comprising a plurality of command terminals receiving the auto-refresh commands, the read commands and the write commands, the command terminals corresponding to the memory areas respectively.

10. The device according to claim 1 ,
wherein the respective refresh start signals have a same period.

11. The device according to claim 1 ,
wherein activation timings of the refresh start signals deviate from one another by the first period.

12. A device comprising, on a single semiconductor chip:
a plurality of memory circuits, each of the memory circuits comprising,
a memory cell array including a plurality of memory cells,
at least one data terminal, and
a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells; and

a refresh control circuit configured to generate a plurality of refresh initiation signals based on an externally-received self-refresh request such that one of the refresh initiation signals takes an active level while remaining one or ones of the refresh initiation signals are taking substantially an inactive level;
each of the memory circuits further comprising a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.

13. The device as claimed in claim 12 , wherein the memory cell array of each of the memory circuits includes a plurality of memory banks each including plural ones of the memory cell arrays, and the refresh circuit of each of the memory circuits performs the data refresh operation on each of the memory banks in sequence.

14. The device as claimed in claim 12 , wherein the refresh control circuit is divided into a plurality of sub-control circuits each generating an associated one of the refresh initiation signals, each of the sub-control circuits is contained in an associated one of the memory circuits.

15. A device comprising:
a first semiconductor chip; and
a second semiconductor chip electrically coupled to the first semiconductor chip;
the second semiconductor chip comprising:
a first memory cell array,
a plurality of first data terminals,
a first data read/write circuit configured to perform data transfer between the first memory cell array and the first data terminals,
a first refresh circuit configured to perform a first data refresh operation on the first memory cell array in response to an active level of a first refresh initiation signal,
a second memory cell array,
a plurality of second data terminals,
a second data read/write circuit configured to perform data transfer between the second memory cell array and the second data terminals,
a second refresh circuit configured to perform a second data refresh operation on the second memory cell array in response to an active level of a second refresh initiation signal, and
a first refresh control circuit configured to respond to an externally-received first refresh command for the first memory cell array and an externally-received second refresh command for the second memory cell array being issued in parallel to each other and produce the first and second refresh initiation signals such that the first refresh initiation signal takes the active level while the second refresh initiation signal is taking substantially an inactive level and the second refresh initiation signal takes the active level while the first refresh initiation signal is taking substantially an inactive level.

16. The device as claimed in claim 15 , wherein the second semiconductor chip is stacked over the first semiconductor chip, and the first semiconductor chip issues the externally-received first and second refresh commands.

17. The device as claimed in claim 16 ,
wherein the device further comprises a third semiconductor chip stacked over the first semiconductor chip; and
wherein the third semiconductor chip comprises:
a third memory cell array,
a plurality of third data terminals electrically connected to the first data terminals of the second semiconductor chip,
a third data read/write circuit configured to perform data transfer between the third memory cell array and the third data terminals,
a third refresh circuit configured to perform a third data refresh operation on the third memory cell array in response to an active level of a third refresh initiation signal,
a fourth memory cell array,
a plurality of fourth data terminals electrically connected to the second data terminals of the second semiconductor chip,
a fourth data read/write circuit configured to perform data transfer between the fourth memory cell ar

Assignees

• Sakakibara Kenichi
• Ishikawa Toru
• Ps4 Luxco Sarl

Inventors

• Sakakibara Kenichi
• Ishikawa Toru

Classifications

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title