Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9679896-B2
Application number	US-201514968297-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 16, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A moisture blocking structure includes an active fin disposed on a sealing region of a substrate, the substrate including a chip region and the sealing region surrounding a periphery of the chip region, the active fin continuously surrounding the chip region and having a winding line shape in a plan view. A gate structure covers the active fin and surrounds the periphery of the chip region. A conductive structure is disposed on the gate structure, the conductive structure surrounding the periphery of the chip region.

First claim

What is claimed is:

1. A moisture blocking structure, comprising:
an active fin disposed on a sealing region of a substrate, the substrate including a chip region and the sealing region surrounding a periphery of the chip region, the active fin continuously surrounding the chip region and having a winding line shape in a plan view;
a gate structure covering the active fin and surrounding the periphery of the chip region; and
a conductive structure disposed on the gate structure, the conductive structure surrounding the periphery of the chip region,
wherein the active fin includes:
a plurality of first portions each extending in a first direction substantially parallel to a top surface of the substrate, the plurality of first portions being disposed in a third direction having an acute angle with the first direction; and
a plurality of second portions each extending in a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction,
wherein each end of each first portion of the plurality of first portions is connected to an end of a corresponding second portion of the plurality of second portions.

2. The moisture blocking structure of claim 1 , further comprising a plurality of active fins,
wherein the gate structure covers two neighboring active fins of the plurality of active fins.

3. The moisture blocking structure of claim 2 , wherein the two neighboring active fins are substantially parallel to each other.

4. The moisture blocking structure of claim 1 , wherein the conductive structure includes
a contact plug disposed on the gate structure, the contact plug surrounding the periphery of the chip region, and
a via disposed on the contact plug, the via surrounding the periphery of the chip region.

5. The moisture blocking structure of claim 1 , further comprising:
a plurality of active fins, a plurality of gate structures, and a plurality of conductive structures; and
a metal layer disposed on the plurality of conductive structures.

6. The moisture blocking structure of claim 1 , further comprising a blocking layer pattern disposed between the gate structure and the conductive structure, the blocking layer pattern including an insulating material.

7. A semiconductor device, comprising:
a substrate having a first region and a second region, wherein the second region is disposed around the first region;
a first active fin disposed on the first region, a second active fin disposed on the second region, and a third active fin disposed on the second region, wherein the second active fin forms a closed loop around the first region, and the third active fin forms a closed loop around the second active fin;
a first conductive structure disposed on the second active fin, wherein the first conductive structure forms a closed loop around the first region;
a first gate structure covering the third active fin, a second conductive structure disposed on the first gate structure, wherein the first gate structure forms a closed loop around the second active fin, and the second conductive structure forms a closed loop around the second active fin.

8. The semiconductor device of claim 7 , further comprising a fourth active fin disposed between the second and third active fins, the fourth active fin forming a closed loop around the second active fin, and a fifth active fin disposed on the second region of the substrate, the fifth active fin forming a closed loop around the third active fin,
wherein the first conductive structure covers the second and fourth active fins, and the second conductive structure covers the third and fifth active fins.

9. The semiconductor device of claim 7 , wherein the second and third active fins each includes a curved or zigzag portion.

10. The semiconductor device of claim 7 , further comprising a second gate structure including a first gate insulation layer pattern and a first gate electrode sequentially stacked on the first active fin.

11. The semiconductor device of claim 7 , wherein the first conductive structure includes a first contact plug disposed on the second active fin, the first contact plug forming a closed loop around the first region, and
a first via disposed on the first contact plug, the first via forming a closed loop around the first region, and
wherein the second conductive structure includes a second contact plug disposed on the first gate structure, the second contact plug forming a closed loop around the second active fin, and
a second via disposed on the second contact plug, the second via forming a closed loop around the second active fin.

12. The semiconductor device of claim 7 , further comprising a plurality of second active fins,
wherein each of first and second ones of the plurality of second active fins have concave portions and convex portions,
and wherein the concave portions of the first one of the plurality of second active fins face the convex portions of the second one of the plurality of second active fins, respectively, and the convex portions of the first one of the plurality of second active fins face the concave portions of the second one of the plurality of second active fins, respectively.

13. The semiconductor device of claim 7 , further comprising a plurality of third active fins,
wherein each of first and second ones of the plurality of third active fins have concave portions and convex portions,
and wherein the concave portions of the first one of the plurality of third active fins face the convex portions of the second one of the plurality of third active fins, respectively, and the convex portions of the first one of the plurality of third active fins face the concave portions of the second one of the plurality of third active fins, respectively.

14. The semiconductor device of claim 7 , further comprising a plurality of first active fins,
wherein each of the first active fins extend in the same direction.

15. The moisture blocking structure of claim 1 , further comprising a plurality of active fins,
wherein each of first and second ones of the plurality of active fins have concave portions and convex portions,
and wherein the concave portions of the first one of the plurality of active fins face the convex portions of the second one of the plurality of active fins, respectively, and the convex portions of the first one of the plurality of active fins face the concave portions of the second one of the plurality of active fins, respectively.

16. The moisture blocking structure of claim 1 , wherein the active fin is a first active fin,
and wherein the semiconductor device further includes a plurality of second active fins disposed on the chip region of the substrate, each of the second active fins extending in a fourth direction.

17. The moisture blocking structure of claim 16 , wherein the gate structure is a first gate structure,
and wherein the semiconductor device further includes a second gate structure on the chip region of the substrate, the second gate structure extending in a fifth direction substantially perpendicular to the fourth direction.

18. A semiconductor device, comprising:
a substrate having a first region and a second region, wherein the second region is disposed around the first region;
a first active fin disposed on the second region and a second active fin disposed on the second region, wherein the first active fin forms a closed loop around the first region, and the second active fin forms a closed loop around the first active fin;
a first conductive structure

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Young-Soo
• Choi Min-Kwon
• Son Yang-Soo
• Kim Hyun-Jo
• Yu Han-Ii

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10D30/6217 Primary

  having non-uniform gate electrodes, e.g. gate conductors having varying doping · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L23/564

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic