Environmental-surrounding-aware OPC

Patent metadata

Field	Value
Publication number	US-9679100-B2
Application number	US-201514831926-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Aug 21, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

First claim

What is claimed is:

1. A method of performing optical proximity correction (OPC), comprising:
receiving an integrated circuit (IC) design layout, the design layout containing a plurality of IC layout patterns, wherein the plurality of IC layout patterns are patterns that cannot be resolved by double patterning;
grouping two or more of the plurality of IC layout patterns;
dissecting or setting target points for the grouped IC layout patterns; and
thereafter performing an OPC process based on the grouped IC layout patterns.

2. The method of claim 1 , wherein the grouping comprises:
identifying IC layout patterns that are nearby one another; and
grouping together at least a subset of the identified IC layout patterns.

3. The method of claim 2 , wherein the grouping further comprises: identifying a zone of interaction between the patterns that are nearby one another.

4. The method of claim 3 , wherein the dissecting or the setting target points are performed within the zone of interaction.

5. The method of claim 4 , wherein the dissecting or setting target points comprises moving dissection locations or target points.

6. The method of claim 4 , wherein the dissecting or setting target points comprises adding one or more auxiliary target points within the zone of interaction.

7. The method of claim 1 , wherein the grouping comprises: grouping IC layout patterns that are: nearby one another, or have substantially different loading.

8. The method of claim 1 , wherein the dissecting or the setting target points comprises dissecting or setting target points asymmetrically for each of the IC layout patterns in the grouped IC layout patterns.

9. The method of claim 1 , further comprising: generating a modified IC design layout based on the OPC process.

10. The method of claim 1 , wherein:
the grouping is performed based on an optical imaging influence exerted among the grouped IC layout patterns; and
the dissecting or setting target points is performed to compensate for the optical imaging influence exerted among the grouped IC layout patterns.

11. A method of performing optical proximity correction (OPC), comprising:
receiving an integrated circuit (IC) design layout, the design layout containing a plurality of IC features that cannot be resolved by double patterning;
identifying a subset of IC features that are located within a predetermined distance from one another or IC features that have substantially different loading;
grouping the subset of the IC features;
specifying dissection locations or target points for the grouped subset of the IC features; and
generating simulated contours for the grouped subset of the IC features.

12. The method of claim 11 , wherein the grouping further comprises: identifying an area of interaction for the grouped subset of the IC features.

13. The method of claim 12 , wherein the specifying comprises specifying dissection locations or target points within the area of interaction.

14. The method of claim 13 , wherein the specifying comprises adding auxiliary target points within the area of interaction.

15. The method of claim 13 , wherein the specifying is performed such that the dissection locations or target points are asymmetrically disposed within each of the IC features in the subset.

16. The method of claim 11 , further comprising: revising the dissection locations or the target points based on the generated simulated contours.

17. The method of claim 11 , further comprising:
generating a modified IC design layout based on the identifying, the grouping, the specifying, and the generating of the simulated contours; and
sending the modified IC design layout to a photomask fabrication facility.

18. A method of performing optical proximity correction (OPC), comprising:
receiving an integrated circuit (IC) design layout, the design layout containing a plurality of polygons that cannot be resolved by double patterning;
determining a zone of interaction for at least a subset of the polygons, wherein the determining comprises identifying polygons that are in close physical proximity or polygons that have substantially different geometric sizes;
dissecting edges or setting target point locations for the subset of the polygons, wherein the dissecting or the setting of the target point locations within the zone of interaction are performed differently than the dissecting or the setting of the target point locations outside the zone of interaction; and
thereafter performing an OPC simulation.

19. The method of claim 18 , further comprising: repeating the dissecting or the setting of the target point locations based on the OPC simulation by modifying dissection or target point locations.

20. The method of claim 18 , further comprising:
generating an output file based on the OPC simulation; and
fabricating a photomask based on the output file.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Wen-Li
• Chih Ming-Hui
• Liu Ru-Gun
• Huang Wen-Chun

Classifications

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F1/72

  Repair or correction of mask defects · CPC title

• G06F17/5081 Primary

  Physics · mapped topic