High breakdown n-type buried layer

Patent metadata

Field	Value
Publication number	US-9673273-B2
Application number	US-201615175192-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Apr 25, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a p-type semiconductor material;
an n-type buried layer disposed in the substrate, the n-type buried layer comprising:
a main layer having a first doping concentration with dopants selected from a group consisting of antimony, arsenic, and combinations thereof, and the main layer having a buried top surface below a top surface of the substrate; and
a lightly-doped layer positioned below the main layer, the lightly-doped layer having a second doping concentration lower than the first doping concentration.

2. The semiconductor device of claim 1 , wherein the p-type semiconductor material has a resistivity of 5 ohm-cm to 10 ohm-cm.

3. The semiconductor device of claim 1 , wherein at least 50 percent of the dopants in the main layer include antimony.

4. The semiconductor device of claim 1 , further comprising:
a deep trench structure extending from the top surface of the substrate through the n-type buried layer to reach a lower layer of the substrate without penetrating through the substrate, the deep trench structure including a dielectric liner coating a bottom portion of the deep trench structure and contacting the substrate.

5. The semiconductor device of claim 4 , wherein the deep trench structure has a closed-loop configuration defined on the top surface of the substrate.

6. The semiconductor device of claim 4 , further comprising:
n-type sinkers extending from the top surface of the substrate and abutting the deep trench structure and the buried top surface of the n-type buried layer.

7. The semiconductor device of claim 1 , further comprising:
an n-type sinker disposed in the substrate, and the n-type sinker extending to the buried top surface of the n-type buried layer, the n-type sinker having a closed-loop configuration.

8. The semiconductor device of claim 1 , wherein:
the first doping concentration is greater than 5×10 18 cm −3 ; and
the second doping concentration ranges from 1×10 16 cm −3 to 1×10 17 cm −3 .

9. The semiconductor device of claim 1 , wherein the first doping concentration is greater than the second doping concentration by at least 50 times.

10. The semiconductor device of claim 1 , further comprising:
an electrode coupled to the n-type buried layer, and configured to bias the n-type buried layer between 80 volts and 110 volts.

11. A semiconductor device, comprising:
a first semiconductor layer including first dopants of a first conductivity type;
a second semiconductor layer positioned on the first semiconductor layer, the second semiconductor layer including second dopants of the first conductivity type, and the second semiconductor layer having a top surface facing away from the first semiconductor layer; and
a buried layer positioned within a junction between the first semiconductor layer and the second semiconductor layer, the buried layer having:
a first buried layer within the first semiconductor layer, the first buried layer including third dopants of a second conductivity type opposite of the first conductivity type, the first buried layer having a first doping concentration; and
a second buried layer positioned on the first buried layer, the second buried layer including fourth dopants of the second conductivity type and at a second doping concentration higher than the first doping concentration.

12. The semiconductor device of claim 11 , wherein the second buried layer extends across the junction between the first semiconductor layer and the second semiconductor layer.

13. The semiconductor device of claim 11 , wherein the second buried layer includes:
a top layer positioned in the second semiconductor layer; and
a bottom layer positioned in the first semiconductor layer, and abutting the top layer.

14. The semiconductor device of claim 11 , wherein:
the first and second dopants each include a p-type semiconductor material; and
the third and fourth dopants each include an n-type semiconductor material.

15. The semiconductor device of claim 11 , wherein:
the third dopants include at least 90 percent of phosphorus; and
the fourth dopants include at least 50 percent of an n-type dopants selected from a group consisting of arsenic, antimony, and combinations thereof.

16. The semiconductor device of claim 11 , further comprising:
a deep trench structure extending from the top surface of the second semiconductor layer through the buried layer to reach the first semiconductor layer without penetrating through the first semiconductor layer, the deep trench structure including a dielectric liner coating a bottom portion of the deep trench structure and contacting the first semiconductor layer.

17. The semiconductor device of claim 11 , further comprising:
a sinker extending from the second semiconductor layer to the buried layer, the sinker having a closed-loop configuration.

18. The semiconductor device of claim 11 , wherein:
the first doping concentration is greater than 5×10 18 cm −3 ; and
the second doping concentration ranges from 1×10 16 cm −3 to 1×10 17 cm −3 .

19. The semiconductor device of claim 11 , wherein the first doping concentration is greater than the second doping concentration by at least 50 times.

20. The semiconductor device of claim 11 , further comprising:
an electrode coupled to the buried layer, and configured to bias the buried layer between 80 volts and 110 volts.

Assignees

• Texas Instruments Inc

Inventors

• Pendharkar Sameer P
• Hu Binghua
• Edwards Henry Litzmann

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title