N/p boundary effect reduction for metal gate transistors
US-2015364459-A1 · Dec 17, 2015 · US
Method for fabricating semiconductor device
US9673053B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9673053-B2 |
| Application number | US-201414549529-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 20, 2014 |
| Priority date | Nov 20, 2014 |
| Publication date | Jun 6, 2017 |
| Grant date | Jun 6, 2017 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating semiconductor device, comprising: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; performing a chemical mechanical polishing (CMP) process to remove part of the second material layer; performing a first etching process to remove the remaining second material layer; and performing a second etching process to remove the stop layer for forming a gate layer. 2. The method of claim 1 , wherein the first etching process comprises an anisotropic etching process. 3. The method of claim 1 , wherein the second etching process comprises an anisotropic etching process.
Assignees
Inventors
Classifications
Planarisation of conductive or resistive materials · CPC title
of conductive or resistive materials · CPC title
- H10D64/01326Primary
Aspects related to lithography, isolation or planarisation of the conductor · CPC title
- H10P52/402Primary
of semiconductor materials · CPC title
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9673053B2 cover?
- A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D64/01326. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).