Superposed structure 3D orthogonal through substrate inductor

Patent metadata

Field	Value
Publication number	US-9666362-B2
Application number	US-201615046302-A
Country	US
Kind code	B2
Filing date	Feb 17, 2016
Priority date	Jul 18, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A three-dimensional ( 3 D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

First claim

What is claimed is:

1. A method for forming a three-dimensional inductor pair, comprising:
providing a substrate, wherein the substrate has a substrate top surface and a substrate bottom surface;
forming in the substrate, in an alignment with a winding section of a first winding axis, a plurality of pairs of first coil via through holes, wherein each pair of first coil via through holes comprises two via through holes spaced symmetrically from the first winding axis by a first horizontal winding radius;
forming in the substrate, in an alignment with a winding section of a second winding axis, a plurality of pairs of second coil via through holes, wherein each pair of second coil via through holes comprises two via through holes spaced symmetrically from the first winding axis by a second horizontal winding radius, wherein the first winding axis is orthogonal to the second winding axis, wherein the first winding axis intersects the second winding axis at an intersection point, and wherein the intersection point is concurrently within the winding section of the first winding axis and the winding section of the second winding axis;
filling the plurality of pairs of first coil via through holes and the plurality of pairs of second via through holes with metal to form, respectively, a plurality of pairs of first coil vias, and a plurality of pairs of second coil vias;
forming a first top metallization, wherein the first top metallization is on the substrate top surface, wherein the first top metallization includes a first coil top offset cross trace, wherein the first coil top offset cross trace is arranged to pass over the first winding axis and to couple a top of a first via of a first pair of first coil vias to a top of a first via of a second pair of first coil vias;
forming a first bottom metallization, wherein the first bottom metallization is on the substrate bottom surface, wherein the first bottom metallization includes a second coil bottom cross trace, wherein the second coil bottom cross trace is arranged to pass under the second winding axis and to couple a bottom of a first via of a first pair of second coil vias to a bottom of the second via of the first pair of second coil vias;
forming a second top metallization, wherein the second top metallization is on the substrate top surface, wherein the second top metallization includes a second coil top offset cross trace, wherein the second coil top offset cross trace is arranged to pass over the second winding axis and over the first coil top offset cross trace and to couple a top of the second via of the first pair of second coil vias to a top of a first via of a second pair of second coil vias; and
forming a second bottom metallization, wherein the second bottom metallization is on the substrate bottom surface, wherein the second bottom metallization includes a first coil bottom cross trace, wherein the first coil bottom cross trace is arranged to pass under the first winding axis and to couple a bottom of a second via of the first pair of first coil vias to a bottom of the first via of the first pair of first coil vias.

2. The method of claim 1 , further comprising:
forming a top dielectric layer, wherein the top dielectric layer is over the first top metallization;
etching clearances through the top dielectric layer, wherein the clearances through the top dielectric layer are located and dimensioned to expose the top of the first via of the first pair of second coil vias and to expose the top of the first via of the second pair of second coil vias;
forming a bottom dielectric layer, wherein the bottom dielectric layer is over the first bottom metallization; and
etching clearances through the bottom dielectric layer, wherein the clearances through the bottom dielectric layer are located and dimensioned to expose the bottom of the second via of the first pair of second coil vias and to expose the bottom of the first via of the first pair of second coil vias.

3. The method of claim 1 ,
wherein the first top metallization includes a first inductor first port and a first inductor second port, and
wherein the first inductor first port is coupled to the top of the second via of the first pair of first coil vias and the first inductor second port is coupled to the top of the first via of the second pair of first coil vias.

4. The method of claim 1 ,
wherein the first coil top offset cross trace is a first coil first top offset cross trace, and the first coil bottom cross trace is a first coil first bottom cross trace,
wherein the first top metallization further includes a first coil second top offset cross trace,
wherein the first coil second top offset cross trace is arranged to pass over the first winding axis and to couple a top of the second via of the second pair of first coil vias to a top of a first via of a third pair of first coil vias,
wherein the first bottom metallization further includes a second coil second bottom cross trace and a second coil third bottom cross trace,
wherein the second coil second bottom cross trace is arranged to pass under the second winding axis and to couple a bottom of the first via of the second pair of second coil vias to a bottom of a second via of the second pair of second coil vias, and
wherein the second coil third bottom cross trace is arranged to pass under the second winding axis and to couple a bottom of a first via of a third pair of second coil vias to a bottom of a second via of the third pair of second coil vias.

5. The method of claim 4 ,
wherein the second coil top offset cross trace is a second coil first top offset cross trace, the second coil bottom cross trace is a second coil first bottom cross trace,
wherein the second top metallization further includes a second coil second top offset cross trace,
wherein the second coil second top offset cross trace is arranged to pass over the second winding axis and to couple a top of the second via of the second pair of second coil vias to a top of a first via of a third pair of second coil vias,
wherein the second bottom metallization further includes a first coil second bottom cross trace and a first coil third bottom cross trace,
wherein the first coil second bottom cross trace is arranged to pass under the first winding axis and to couple a bottom of the first via of the second pair of first coil vias to a bottom of the second via of the second pair of first coil vias, and
wherein the first coil third bottom cross trace is arranged to pass under the first winding axis and to couple a bottom of the first via of the third pair of first coil vias to a bottom of a second via of the third pair of first coil vias.

6. A method for forming a three-dimensional inductor pair, comprising
providing a substrate, wherein the substrate has a substrate top surface and a substrate bottom surface;
forming in the substrate, in an alignment with a winding section of a first winding axis, a plurality of pairs of first coil via through holes, wherein each pair of first coil via through holes comprises two via through holes spaced symmetrically from the first winding axis by a first horizontal winding radius;
forming in the substrate, in an alignment with a winding section of a second winding axis, a plurality of pairs of second coil via through holes, wherein each pair of second coil via through holes comprises two via through holes spaced symmetrically from the second winding axis by a second horizontal winding radius, wherein the first winding axis is orthogonal to the second winding axis, wherein the first winding axis intersects the second winding axis at an intersection point, and wherein the intersection point is concurrently within the winding section of the first winding axis and the winding section of the second winding axis;
fillin

Assignees

• Qualcomm Inc

Inventors

• Berdy David Francis
• Zuo Chengjie
• Kim Daeik Daniel
• Yun Changhan Hobie
• Velez Mario Francisco
• Mikulka Robert Paul
• Kim Jonghae

Classifications

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H01L23/5227

  Electricity · mapped topic

• H01F2017/004

  with the coil helically wound around an axis without a core · CPC title

• H01F27/2804

  Printed windings · CPC title

• H01L28/10

  Electricity · mapped topic