Data strobe signal generation for flash memory

Patent metadata

Field	Value
Publication number	US-9251906-B1
Application number	US-201514715544-A
Country	US
Kind code	B1
Filing date	May 18, 2015
Priority date	May 18, 2015
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method and circuit for generating a shifted strobe signal for sampling data read from a memory device includes generating an instantiation of a shifted strobe signal by applying both a coarse adjustment delay value and a fine adjustment delay value to a clock. Data read from a predetermined, programmed memory location or locations of the memory device is sampled using the shifted strobe signal. At least one of the applying steps is repeated and the read data is sampled again using the current instantiation of the shifted strobe signal. The process is repeated until the current instantiation of the shifted strobe signal is aligned with a valid data window of the memory device. The method can be used in both single data rate and double data rate applications.

First claim

The invention claimed is:

1. A method for generating a shifted strobe signal for sampling data read from a memory device, the method comprising:
(a) generating a shifted strobe signal by applying a coarse adjustment delay value and a fine adjustment delay value to a clock signal;
(b) reading data stored in a predetermined memory location of the memory device that is pre-programmed with known data;
(c) sampling the read data using the shifted strobe signal;
(d) determining whether the sampled data matches the known data; and
(e) updating one or both of the coarse and fine adjustment delay values and repeating steps (a)-(d) until the sampled data matches the known data, whereby the shifted data strobe is aligned with a valid data window of the memory device.

2. The method of claim 1 , wherein, after the fine adjustment delay value is incremented through a predetermined range of fine adjustment delay values, the fine adjustment delay value is reset to a smaller fine adjustment delay value, and the coarse adjustment delay value is incremented to a next larger delay value.

3. The method of claim 2 , wherein resetting the fine adjustment delay value to a smaller delay value resets the fine adjustment delay value to a predetermined minimum fine adjustment delay value.

4. The method of claim 1 , further comprising:
when the sampled data matches the known data, storing the fine adjustment delay value and the coarse adjustment delay value for repeated use in generating the shifted strobe signal for sampling unknown data read from the memory device.

5. The method of claim 1 , wherein step (e) comprises:
updating one or both of the coarse and fine adjustment delay values until matches occur in K>1 iterations of steps (a)-(d); and
further comprising storing the coarse and fine adjustment delay values for a middle one of the K iterations for repeated use in generating the shifted strobe signal for sampling unknown data read from the memory device.

6. The method of claim 5 , wherein the fine adjustment delay value matches occur at multiple fine adjustment delay values and a single coarse adjustment delay value.

7. The method of claim 1 , wherein the memory device is a flash memory device.

8. The method of claim 1 , further comprising deglitching the shifted strobe signal.

9. The method of claim 1 , wherein the method is invoked by one of powering-up the memory device, passage of a predetermined period of time from a previous execution of the method, and during a slow background operation.

10. The method of claim 1 , wherein the method is invoked by a monitored parameter on the memory device deviating from a predetermined parameter value by a predetermined differential value.

11. The method of claim 10 , wherein the monitored parameter is one of temperature and voltage.

12. A circuit for generating a shifted strobe signal for sampling data read from a memory device, the circuit comprising:
a coarse adjustment circuit for applying a coarse adjustment delay value to a clock signal;
a fine adjustment circuit for applying a fine adjustment delay value to the clock signal; and
a control circuit for controlling the coarse and fine adjustment circuits to systematically sequence through combinations of the coarse adjustment delay value and the fine adjustment delay value incrementing the fine adjustment value through a predetermined range of values and upon reaching an end of the range of fine adjustment values resetting the fine adjustment delay value to a lesser value and incrementing the coarse adjustment delay value to a next higher value until a current instantiation of the shifted data strobe is aligned with a valid data window of the memory device.

13. The circuit of claim 12 , wherein the control circuit samples data read from the memory device using the generated shifted strobe signal.

14. The circuit of claim 13 , wherein the control circuit compares the sampled data to known data stored in a predetermined, programmed memory location of the memory device.

15. The circuit of claim 12 , further comprising:
a monitoring circuit for monitoring a parameter and deviation of the parameter from a set point, the monitoring circuit for invoking a calibration process upon the parameter deviating from the set point by a predetermined differential value.

16. The circuit of claim 12 , further comprising:
a timer circuit for measuring elapsed time from initiation of a calibration process, wherein the timer initiates a subsequent calibration process upon passage of a predetermined time period.

17. A circuit for generating a shifted strobe signal for sampling data read from a memory device, the circuit comprising:
a coarse adjustment circuit for applying a coarse adjustment delay value to a clock signal;
a fine adjustment circuit for applying a fine adjustment delay value to the clock signal;
a control circuit for controlling the coarse and fine adjustment circuits to systematically sequence through combinations of the coarse adjustment delay value and the fine adjustment delay value incrementing the fine adjustment value through a predetermined range of values and upon reaching an end of the range of fine adjustment values resetting the fine adjustment delay value to a lesser value and incrementing the coarse adjustment delay value to a next higher value until a current instantiation of the shifted data strobe aligns with a valid data window of the memory device;
a monitoring circuit for monitoring a parameter of the memory device and deviation of the parameter from a set point, the monitoring circuit for invoking a calibration process upon the parameter deviating from the set point by a predetermined differential parameter value; and
a timer circuit for measuring elapsed time from initiation of a calibration process of the memory device, the timer for initiating a subsequent calibration process upon passage of a predetermined time period.

Assignees

• Freescale Semiconductor Inc

Inventors

• Jain Aarul
• Agarwal Neha
• Pandey Rakesh
• Sakalley Deboleena Minz

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title