Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9659958-B2
Application number	US-201615291521-A
Country	US
Kind code	B2
Filing date	Oct 12, 2016
Priority date	Oct 13, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a lower selection line and at least one upper selection line stacked on a substrate in a first direction crossing to a top surface of the substrate;
a cell gate structure between the lower selection line and the at least one upper selection line, the cell gate structure including cell gate electrodes stacked in the first direction;
a lower dummy structure between the lower selection line and the cell gate structure, the lower dummy structure including a lower dummy gate line spaced apart from a lowermost one of the cell gate electrodes in the first direction by a first distance; and
an upper dummy structure between the at least one upper selection line and the cell gate structure, the upper dummy structure including an upper dummy gate line spaced apart from an uppermost one of the cell gate electrodes in the first direction by a second distance, wherein the lower dummy gate line and the upper dummy gate line are immediately adjacent to the lowermost cell gate electrode and the uppermost cell gate electrode, respectively, wherein the cell gate electrodes are spaced apart from each other in the first direction by a third distance, and wherein each of the first and second distances is greater than the third distance.

2. The device as claimed in claim 1 , wherein:
the upper dummy structure includes a plurality of upper dummy gate lines stacked in the first direction, and
the upper dummy gate line immediately adjacent to the uppermost cell gate electrode is a lowermost one of the upper dummy gate lines.

3. The device as claimed in claim 2 , wherein the upper dummy gate lines are spaced apart from each other in the first direction by the second distance.

4. The device as claimed in claim 2 , wherein:
the at least one upper selection line is spaced apart from an uppermost one of the upper dummy gate lines in the first direction by a fourth distance, and
the fourth distance is greater than the second distance.

5. The device as claimed in claim 4 , further comprising:
a plurality of upper selection lines,
wherein the upper selection lines are stacked in the first direction on the upper dummy structure and wherein a lowermost one of the upper selection lines is spaced apart from the uppermost upper dummy gate line by the fourth distance.

6. The device as claimed in claim 4 , wherein:
the lower dummy structure includes a plurality of lower dummy gate lines stacked in the first direction, and
the lower dummy gate line immediately adjacent to the lowermost cell gate electrode is an uppermost one of the lower dummy gate lines.

7. The device as claimed in claim 6 , wherein the lower dummy gate lines are spaced apart from each other in the first direction by the first distance.

8. The device as claimed in claim 6 , wherein:
the lower selection line is spaced apart from a lowermost one of the lower dummy gate lines in the first direction by a fifth distance, and
the fifth distance is greater than the first distance.

9. The device as claimed in claim 8 , wherein the fifth distance is greater than the fourth distance.

10. The device as claimed in claim 9 , wherein the first distance is substantially equal to the second distance.

11. The device as claimed in claim 1 , wherein:
the lower selection line, the at least one upper selection line, the cell gate structure, the lower dummy structure, and the upper dummy structure are in a stack structure, and
the stack structure extends in a second direction parallel to the top surface of the substrate.

12. The device as claimed in claim 11 , further comprising:
a channel structure penetrating the stack structure and connected to the substrate.

13. The device as claimed in claim 11 , further comprising:
insulating layers in the stack structure and extending in the second direction; and
a lower insulating layer between the substrate and the stack structure,
wherein the at least one upper selection line, the upper dummy structure, the cell gate structure, the lower dummy structure, and the lower selection line are separated from each other by the insulating layers interposed therebetween, wherein the insulating layers and the lower insulating layer have thicknesses in the first direction, respectively, and wherein the thickness of the lower insulating layer is less than the thicknesses of the insulating layers.

14. The device as claimed in claim 12 , wherein:
the channel structure includes a lower semiconductor pattern penetrating a portion of the substrate and an upper semiconductor pattern spaced apart from the substrate with the lower semiconductor pattern therebetween,
the lower dummy structure includes a plurality of lower dummy gate lines stacked in the first direction,
the lower dummy gate line immediately adjacent to the lowermost cell gate electrode is an uppermost one of the lower dummy gate lines, and
a top surface of the lower semiconductor pattern is at a level between a top surface of the lower selection line and a bottom surface of a lowermost one of the lower dummy gate lines.

15. The device as claimed in claim 14 , wherein the upper semiconductor pattern includes:
a first semiconductor pattern covering an inner sidewall of the stack structure and spaced apart from the lower semiconductor pattern; and
a second semiconductor pattern covering an inner sidewall of the first semiconductor pattern and contacting the lower semiconductor pattern.

16. A three-dimensional (3D) semiconductor memory device, comprising:
a first selection line on a substrate;
a cell gate structure between the substrate and the first selection line, the cell gate structure including a plurality of cell gate electrodes stacked in a first direction crossing a top surface of the substrate; and
a first dummy structure between the first selection line and the cell gate structure, the first dummy structure including at least one first dummy gate line, wherein the cell gate electrodes are separated from each other by first insulating layers therebetween, wherein the first dummy structure and the cell gate structure are separated from each other by a second insulating layer therebetween, wherein the first insulating layers and the second insulating layer have thicknesses in the first direction, respectively, and wherein the thickness of the second insulating layer is greater than the thicknesses of the first insulating layers.

17. The device as claimed in claim 16 , wherein:
the first selection line and the first dummy structure are separated from each other by a third insulating layer interposed therebetween,
the third insulating layer has a thickness in the first direction, and
the thickness of the third insulating layer is greater than the thickness of the second insulating layer.

18. The device as claimed in claim 17 , further comprising:
a second selection line between the substrate and the cell gate structure; and
a second dummy structure between the second selection line and the cell gate structure, the second dummy structure including at least one second dummy gate line, wherein the second dummy structure and the cell gate structure are separated from each other by a fourth insulating layer therebetween, wherein the fourth insulating layer has a thickness in the first direction, and wherein the thickness of the fourth insulating layer is greater than the thicknesses of the first insulating layers.

19. The device as claimed in claim 18 , wherein:
the second selection line and the second dumm

Assignees

• Samsung Electronics Co Ltd
• Samsung Elctronics Co Ltd

Inventors

• Lee Jung Hoon
• Rho Keejeong
• Park Sejun
• Shin Jinhyun
• Lee Dong-Sik
• Lee Woong-Seop

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title