Vertical NAND device with shared word line steps
US-9224747-B2 · Dec 29, 2015 · US
Method of manufacturing a non-volatile memory device having a vertical structure
US8927366B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8927366-B2 |
| Application number | US-201213610344-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 11, 2012 |
| Priority date | Oct 11, 2011 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
First claim
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What is claimed is: 1. A method of manufacturing a non-volatile memory device, the method comprising: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming a…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H01L27/11556Primary
Electricity · mapped topic
Electricity · mapped topic
- H10B41/27Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8927366B2 cover?
- A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side …
- Who is the assignee on this patent?
- Lee Sung-Hae, Hwang Ki-Hyun, Kim Jin-Gyun, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H01L27/11556. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).