Memory system and operation method thereof

Patent metadata

Field	Value
Publication number	US-2016259585-A1
Application number	US-201514743947-A
Country	US
Kind code	A1
Filing date	Jun 18, 2015
Priority date	Mar 6, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

A memory system may include a command storage unit for storing maximum N commands received from a host, K memory devices each for storing maximum M commands based on the maximum N commands and performing each set operation in response to the stored maximum M commands in order of input, and a resetting unit for resetting execution sequences of the maximum N commands based on execution information regarding each of the maximum N commands and the maximum M commands in each of the K memory devices whenever the commands received from the host are stored in the command storage unit, and distributing the N commands to the K memory devices. The execution information includes a logical address, a physical address, a length, and a use time of a corresponding command.

First claim

What is claimed is:

1 . A memory system comprising:
a command storage unit suitable for storing maximum N commands received from a host; K memory devices each suitable for storing maximum M commands based on the maximum N commands and performing each set operation in response to the stored maximum M commands in order of input; and a resetting unit suitable for resetting execution sequences of the maximum N commands based on execution information regarding each of the maximum N commands and the maximum M commands in each of the K memory devices whenever the commands received from the host are stored in the command storage unit, and distributing the N commands to the K memory devices, wherein the execution information comprises a logical address, a physical address, a length, and a use time of a corresponding command.

2 . The memory system of claim 1 , wherein, when the length of the command that has been most recently received from the host and stored in the command storage unit is greater than a set length, the resetting unit excludes the command from a target whose execution sequence is to be reset, sets the excluded command to an exclusion command, and resets execution sequences of remaining (N−1) commands.

3 . The memory system of claim 2 , wherein, after distributing all the remaining (N−1) commands to the K memory devices, the resetting unit distributes the exclusion command to the K memory devices and distributes a command received from the host after the exclusion command.

4 . The memory system of claim 1 , wherein the resetting unit is suitable for:
classifying the K memory devices into a first resetting memory device having a high first priority and a second resetting memory device having a low first priority based on a time required to use all the maximum M commands stored in each of the K memory devices, and setting commands that belong to the maximum N commands and correspond to the first resetting memory device to first resetting commands, and setting commands that belong to the maximum N commands and correspond to the second resetting memory device to second resetting commands.

5 . The memory system of claim 4 , wherein the resetting unit is suitable for:
setting one or more memory devices that need a relatively short time to use all the maximum M commands stored in each of the K memory devices to the first resetting memory device, and setting remaining memory devices except for the first resetting memory device to the second resetting memory device.

6 . The memory system of claim 4 , wherein the resetting unit is suitable for:
classifying the one or more first resetting commands into a third resetting command having a high second priority and a fourth resetting command having a low second priority based on a correlation between values of the physical addresses of the maximum M commands stored in each of the one or more first resetting memory devices and values of the physical addresses of the one or more first resetting commands; advancing an execution sequence of the third resetting command more than an execution sequence of the fourth resetting command; and setting the first resetting memory device corresponding to the third resetting command to a third resetting memory device, and setting the first resetting memory device corresponding to the fourth resetting command to a fourth resetting memory device.

7 . The memory system of claim 6 , wherein the resetting unit is suitable for:
setting the first resetting command that corresponds to where the values of the physical addresses of the one or more first resetting commands are consecutive and have an identical value, to the third resetting command, based on the values of the physical addresses of the M commands stored in each of the one or more first resetting memory devices, and setting the first resetting command that corresponds to where the values of the physical addresses of the one or more first resetting commands are not consecutive and do not have an identical value, to the fourth resetting command.

8 . The memory system of claim 7 , wherein the resetting unit is suitable for:
classifying the one or more fourth resetting commands into a fifth resetting command having a high third priority and a sixth resetting command having a low third priority based on a number of commands stored in each of the one or more fourth resetting memory devices, and advancing an execution sequence of the fifth resetting command more than an execution sequence of the sixth resetting command.

9 . The memory system of claim 8 , wherein the resetting unit is suitable for:
setting a fourth resetting command that belongs to the one or more fourth resetting commands and that corresponds to the fourth resetting memory device in which a relatively small number of commands have been stored, to the fifth resetting command, and setting remaining fourth resetting commands except for the fifth resetting command to the sixth resetting command.

10 . The memory system of claim 8 , wherein, when the resetting unit classifies two or more commands of the maximum N commands into the sixth resetting commands, execution sequences of the two or more sixth resetting commands are determined in order of input.

11 . The memory system of claim 8 , wherein the resetting unit combines two or more commands that belong to the maximum N commands and that have values of consecutive logical addresses into a group and simultaneously applies control of the first to the third priorities to the group.

12 . The memory system of claim 11 , wherein the resetting unit controls execution sequences of the two or more commands included in the group so that a command having a value of a former logical address is first used, a command having a value of a latter logical address is later used, and the commands are always consecutively used.

13 . The memory system of claim 1 , wherein, when a command received from the host is stored in the command storage unit and a set number of commands or more have been stored in the command storage unit, the resetting unit resets the execution sequences of the maximum N commands stored in the command storage unit and distributes the maximum N commands to the K memory devices.

14 . An operation method of a memory system comprising K memory devices each suitable for storing maximum M commands based on maximum N commands received from a host and performing each set operation in response to the maximum M commands in order of input, the operation method comprises:
sequentially storing the maximum N commands from the host in a set storage space; and resetting execution sequences of the maximum N commands stored in the set storage space based on execution information regarding each of the maximum N commands stored in the set storage space and the maximum M commands stored in each of the K memory devices whenever the commands received from the host are stored in the set storage space, and distributing the reset maximum N commands to the K memory devices, wherein the execution information comprises a logical address, a physical address, a length, and a use time of a corresponding command.

15 . The operation method of claim 14 , wherein the resetting of the execution sequences of the maximum N commands and the distributing of the reset maximum N commands to the K memory devices comprise:
setting the command most recently received from the host and stored in the set storage space to an exclusion command when the length of the most recently stored command is greater than a set length; distributing remaining (N−1) commands that are stored in

Assignees

• Sk Hynix Inc

Inventors

• Park Jong-Ju

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G06F9/3816

  Instruction alignment, e.g. cache line crossing · CPC title

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F9/3004

  to perform operations on memory · CPC title