Semiconductor device and method for forming the same

Patent metadata

Field	Value
Publication number	US-9230793-B2
Application number	US-201414197170-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Oct 17, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate including a cell region and a peripheral region;
a Silicon-Metal-Silicon (SMS)-structured wafer provided in the cell region and including a stacked structure of a first silicon substrate, a metal layer, a metal silicide layer, and a second silicon substrate; and
a Silicon On Insulator (SOI)-structured wafer provided in the peripheral region and including a stacked structure of the first silicon substrate, a first silicon insulation film on an upper surface of the first silicon substrate, the metal layer, the second silicon substrate, and a second silicon insulation film on a lower surface of the second silicon substrate,
wherein the metal layer extends across the SOI-structured wafer and the SMS-structured wafer,
wherein the second silicon insulation film is disposed between the metal layer and the second silicon substrate,
wherein the metal silicide layer is disposed over the metal layer that extends across the SMS-structured wafer; and
wherein the second silicon insulation film of the SOI-structured wafer is coplanar with the metal silicide layer of the SMS-structured wafer.

2. The semiconductor device according to claim 1 , wherein the metal silicide layer is formed over the metal layer.

3. The semiconductor device according to claim 1 , wherein the metal layer includes a tungsten (W) material.

4. The semiconductor device according to claim 1 , further comprising:
a silicon oxide film and a glue layer formed over the first silicon substrate in the cell region and in the peripheral region.

5. The semiconductor device according to claim 2 , wherein a distance between an upper surface of the first silicon substrate and an upper surface of the second insulation film is the same as a distance between the upper surface of the first silicon substrate and an upper surface of the metal silicide layer.

6. The semiconductor device according to claim 1 , further comprising:
an alignment key formed in the second silicon substrate of the peripheral region.

7. A semiconductor device comprising:
a Silicon-Metal-Silicon (SMS)-structured cell region including a stacked structure of a first silicon substrate, a metal layer, a metal silicide layer, and a second silicon substrate;
a Silicon On Insulator (SOI)-structured peripheral region including a stacked structure of the first silicon substrate, a first silicon insulation film on an upper surface of the first silicon substrate, the metal layer, the second silicon substrate, and a second silicon insulation film on a lower surface of the second silicon substrate;
a line-shaped buried bit line formed over the first silicon substrate of the cell region and including the metal layer;
a plurality of pillar patterns formed over the buried bit line; and
a gate formed at a sidewall of each pillar pattern so as to interconnect the plurality of pillar patterns,
wherein the metal layer extends across the SMS-structured cell region and the SOI-structured peripheral region,
wherein the second silicon insulation film is disposed between the metal layer and the second silicon substrate,
wherein the metal silicide layer is disposed over the metal layer that extends across the SMS-structured cell region, and
wherein the second silicon insulation film of the SOI-structured wafer peripheral region is coplanar with the metal silicide layer of the SMS-structured cell region.

8. The semiconductor device according to claim 7 , wherein the metal layer includes tungsten (W).

9. The semiconductor device according to claim 7 , further comprising:
a glue layer formed below the metal layer,
wherein the metal silicide layer is formed over the metal layer.

10. The semiconductor device according to claim 9 , wherein the glue layer includes a titanium nitride (TiN) film, and the metal silicide layer includes a cobalt silicide material.

11. The semiconductor device according to claim 7 , wherein the gate is formed in a line shape extending along a direction perpendicular to the buried bit line.

12. The semiconductor device according to claim 7 , further comprising:
an alignment key formed in the second silicon substrate in the peripheral region.

13. The semiconductor device according to claim 7 , further comprising:
a peri-gate structure formed over the second silicon substrate in the peripheral region.

14. The semiconductor device of claim 9 , wherein an upper surface of the metal silicide layer is coplanar with an upper surface of the second silicon insulation film.

15. A semiconductor device comprising:
a Silicon-Metal-Silicon (SMS) cell region including a stacked structure of:
a first silicon substrate;
a first insulation layer disposed over the first silicon substrate;
a metal layer disposed over the first insulation layer;
a metal silicide layer disposed over the metal layer; and
a second silicon substrate disposed over the metal layer, and

a Silicon On Insulator (SOI) peripheral region including a stacked structure of:
the first silicon substrate;
the metal layer disposed over the first insulation layer;
a second insulation layer disposed over the metal layer; and
the second silicon substrate disposed over second insulation layer,

wherein the metal layer extends across the SMS cell region and the SOI peripheral region,
wherein the metal silicide layer is disposed over the metal layer that extends across the SMS cell region,
wherein the second insulation layer of the SOI peripheral region is coplanar with the metal silicide layer SMS cell region.

16. The semiconductor device of claim 15 , wherein a thickness of the second insulation layer and the metal layer in the SOI peripheral region is the same as a thickness of the metal layer and the metal silicide layer in the SMS region.

17. The semiconductor device of claim 15 , wherein an upper surface of the metal silicide layer is coplanar with an upper surface of the second insulation layer.

18. The semiconductor device of claim 15 , wherein an alignment key protrudes from the second insulation layer through the second silicon substrate.

19. The semiconductor device of claim 18 , wherein the alignment key and the second insulation layer are a same material.

20. The semiconductor device of claim 15 , further comprising a glue layer disposed between the first insulation layer and the metal layer.

Assignees

• Sk Hynix Inc

Inventors

• Sung Min Chul

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P10/12

  Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914) · CPC title