Manufacturing method of circuit substrate

Patent metadata

Field	Value
Publication number	US-9655254-B2
Application number	US-201213551586-A
Country	US
Kind code	B2
Filing date	Jul 17, 2012
Priority date	Apr 20, 2010
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

First claim

What is claimed is:

1. A method for manufacturing a circuit substrate, comprising:
bonding peripheries of two metal layers directly to form a sealed area;
forming at least a through hole passing through the sealed area, and wherein an area of the through hole is smaller than an area of the sealed area;
forming two first insulating layers on the two metal layers and forming two inner conductive layers on the two first insulating layers, wherein an area of each of the two first insulating layers is larger than an area of each of the two metal layers;
laminating the two first insulating layers and the two inner conductive layers and the two metal layers bonded with each other being embedded in the two first insulating layers, wherein portions of the two first insulating layers fill in the through hole when the two first insulating lavers are laminated;
patterning the two inner conductive layers, forming two second insulating layers on the two inner conductive layers, and forming two outer conductive layers on the two second insulating layers;
laminating the second insulating layers and the two outer conductive layers and the two inner conductive layers being embedded in the second insulating layers; and
separating the sealed area of the two metal layers to form two separated circuit substrates by removing a region of the sealed area.

2. The method for manufacturing a circuit substrate of claim 1 , wherein the method for bonding the peripheries of the two metal layers comprises an electric welding process or a spot-welding process.

3. The method for manufacturing a circuit substrate of claim 1 , wherein after separating the sealed area of the two metal layers, the method further comprises:
removing a part of the first and second insulating layers, a part of the metal layer, and a part of the outer conductive layer to form a plurality of blind holes exposing the inner conductive layer; and
forming a conductive material in the blind holes and on remaining portions of the metal layer and the outer conductive layer.

4. The method for manufacturing a circuit substrate of claim 3 , wherein after forming the conductive material, the method further comprises patterning the conductive material, the metal layer, and the outer conductive layer.

Assignees

• Huang Tzu-Wei
• Subtron Technology Co Ltd

Inventors

• Huang Tzu-Wei

Classifications

• H05K2201/09527

  Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms · CPC title

• B32B37/02 Primary

  characterised by a sequence of laminating steps, e.g. by adding new layers at consecutive laminating stations · CPC title

• B23K2201/42

  Operations & Transport · mapped topic

• H05K3/0097

  Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence) · CPC title

• B32B2311/00

  Metals, their alloys or their compounds · CPC title