Electronic device and method of manufacturing the same
US-2024404904-A1 · Dec 5, 2024 · US
Method of forming wafer-level molded structure for package assembly
US9117939B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9117939-B2 |
| Application number | US-201414224921-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 25, 2014 |
| Priority date | Aug 26, 2009 |
| Publication date | Aug 25, 2015 |
| Grant date | Aug 25, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming an integrated circuit structure, the method comprising: bonding top dies onto a bottom wafer; molding a first molding material onto and in between the top dies and the bottom wafer; sawing the bottom wafer, the top dies and the first molding material to form molding units, wherein each of the molding units comprises one of the top dies and a bottom die sawed from the bottom wafer; bonding one of the molding units onto a package subs…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9117939B2 cover?
- A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bot…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W74/01. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 25 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).