Level shifter circuit

Patent metadata

Field	Value
Publication number	US-9654087-B1
Application number	US-201615177544-A
Country	US
Kind code	B1
Filing date	Jun 9, 2016
Priority date	Jun 9, 2016
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

First claim

What is claimed is:

1. A high voltage level shifter configured to translate an input signal from a low-side low voltage domain to a high-side low voltage domain, the high voltage level shifter comprising:
a first high voltage level shifter device, wherein the first high voltage level shifter device comprises a first high-side terminal, a first low-side terminal, and a first control terminal, and wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal;
a second high voltage level shifter device, wherein the second high voltage level shifter device comprises a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal;
a low-side control circuit configured to drive the first control terminal and the second control terminal, wherein the low-side control circuit is further configured to drive, in response to the input signal, one of the first high voltage level shifter device and the second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state;
a high-side receiver circuit configured to set a state of a high-side output signal in response to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state;
wherein the high-side receiver circuit is configured to monitor a first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and
wherein the low-side control circuit is configured to control a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state in response to a second difference between the first current and the second current monitored flowing out of the first low-side terminal and the second low-side terminal.

2. The high voltage level shifter of claim 1 , wherein each of the low-side low voltage domain and the high-side low voltage domain comprises a positive rail and a negative rail;
the first high-side terminal of the first high voltage level shifter device is connected to the positive rail of the high-side domain via a first high-side current sensing device;
the second high-side terminal of the second high voltage level shifter device is connected to the positive rail of the high-side domain via a second high-side current sensing device;
the first low-side terminal of the first high voltage level shifter device is connected to the negative rail of the low-side domain via a first low-side current sensing device; and
the second low-side terminal of the second high voltage level shifter device is connected to the negative rail of the low-side domain through a second low-side current sensing device.

3. The high voltage level shifter of claim 2 ,
wherein each of the first high-side current sensing device and the second high-side current sensing device comprise a resistor of a first value;
wherein each of the first low-side current sensing device and the second low-side current sensing device comprise a resistor of a second value; and
wherein the first value and the second value have a predetermined ratio.

4. The high voltage level shifter of claim 3 , wherein the predetermined ratio is substantially equal to 1.

5. The high voltage level shifter of claim 2 , wherein the high-side receiver circuit comprises a first high-side cross-coupled device and a second high-side cross-coupled device, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device comprises:
a control terminal;
an output terminal; and
a common terminal;
wherein the common terminal of the first high-side cross-coupled device is connected to the control terminal of the second high-side cross-coupled device and the first high-side terminal of the first high voltage level shifter device; and
wherein the common terminal of the second high-side cross-coupled device is connected to the control terminal of the first high-side cross-coupled device and the second high-side terminal of the second high voltage level shifter device.

6. The high voltage level shifter of claim 2 , wherein the low-side control circuit comprises a first low-side cross-coupled device and a second cross-coupled device, wherein each of the first low-side cross-coupled device and the second cross-coupled device comprise:
a control terminal;
an output terminal; and
a common terminal;
wherein the common terminal of the first low-side cross-coupled device is connected to the control terminal of the second low-side cross-coupled device and to the first low-side terminal of the first high voltage level shifter device; and
wherein the common terminal of the second low-side cross-coupled device is connected to the control terminal of the first low-side cross-coupled device and to the second low-side terminal of the second high voltage level shifter device.

7. The high voltage level shifter of claim 2 , wherein a monolithic integrated circuit comprises the high voltage level shifter, and wherein the high-side receiver circuit is isolated from a substrate of the monolithic integrated circuit by an n-doped well connected to the positive rail of the high-side domain.

8. The high voltage level shifter of claim 7 ,
wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device is a vertical bipolar transistor;
wherein each corresponding control terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a base terminal of the vertical bipolar transistor;
wherein each corresponding common terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is an emitter terminal of the vertical bipolar transistor;
wherein each corresponding output terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a collector terminal of the vertical bipolar transistor; and
wherein each of an emitter region and a base region of the vertical bipolar transistor has no direct PN junction to the n-doped well.

9. The high voltage level shifter of claim 7 ,
wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device is a vertical MOS transistor;
wherein each corresponding control terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a gate terminal of the vertical MOS transistor;
wherein each corresponding common terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a source terminal of the vertical MOS transistor;
wherein each corresponding output terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a drain terminal of the vertical MOS transistor; and
wherein a source region of the vertical MOS transistor has no direct PN junction to the n-doped well.

10. A method comprising:
receiving, via a low-side control circuit of a high voltage level shifter, an input signal from a low-side low voltage domain;
driving, by the low-side control circuit and in response

Assignees

• Infineon Technologies Austria Ag

Inventors

• Feldtkeller Martin

Classifications

• H03K19/017518 Primary

  using a combination of bipolar and field effect transistors [BIFET] · CPC title

• H03K3/356086 Primary

  with additional means for controlling the main nodes (H03K3/356104, H03K3/3562 take precedence) · CPC title

• H03K3/2885

  the input circuit having a differential configuration · CPC title