Transmitter circuit and receiver circuit for operating under low voltage

Patent metadata

Field	Value
Publication number	US-9917589-B2
Application number	US-201615392554-A
Country	US
Kind code	B2
Filing date	Dec 28, 2016
Priority date	Feb 2, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

First claim

What is claimed is:

1. A transmitter circuit comprising:
a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit;
a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit;
a level shifter configured to convert a voltage level of the logic signal to a level of the first voltage; and
a multiplexer circuit between the level shifter and the pre-driver circuit, the multiplexer circuit configured to receive the logic signal and the converted logic signal having the first voltage and provide one of the logic signal or the converted logic signal to the pre-driver circuit according to a mode control signal, the mode control signal determined according to a transmission frequency of data transmitted/received to/from the input/output pad.

2. The transmitter circuit of claim 1 , wherein the main-driver circuit comprises:
a PMOS transistor configured to pull up a voltage of the input/output pad to the second voltage by the first signal;
a first resistor connected between the PMOS transistor and the input/output pad;
an NMOS transistor configured to pull down the voltage of the input/output pad to a third voltage by the first signal; and
a second resistor connected between the NMOS transistor and the input/output pad.

3. The transmitter circuit of claim 1 , wherein the main-driver circuit comprises:
a first NMOS transistor configured to pull up a voltage of the input/output pad to the second voltage by the first signal;
a first resistor connected between the first NMOS transistor and the input/output pad;
an inverter configured to generate an inverted signal by inverting the first signal;
a second NMOS transistor configured to pull down the voltage of the input/output pad to a third voltage by the inverted signal; and
a second resistor connected between the second NMOS transistor and the input/output pad.

4. A transmitter circuit comprising:
a pre-driver circuit configured to receive a logic signal from a logic circuit and generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit;
a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit;
a level shifter configured to convert a voltage level of the first signal to the second voltage; and
a multiplexer circuit between the level shifter and the main-driver circuit, the multiplexer circuit configured to receive the first signal and the converted first signal having the second voltage and provide one of the first signal or the converted first signal to the main-driver circuit according to a mode control signal, the mode control signal determined according to a transmission frequency of data transmitted/received to/from the input/output pad.

5. An interface circuit comprising:
a transmitter including,
a pre-driver circuit configured to receive a logic signal from a logic circuit and generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit,
a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit,
a level shifter configured to convert a voltage level of the logic signal to a level of the first voltage, and
a multiplexer circuit between the level shifter and the pre-driver circuit, the multiplexer circuit configured to receive the logic signal and the converted logic signal having the first voltage and provide one of the logic signal or the converted logic signal to the pre-driver circuit according to a mode control signal, the mode control signal determined according to a transmission frequency of data transmitted/received to/from the input/output pad; and

a receiver including,
a first input buffer configured to be driven by the first voltage to receive input data of a low-frequency band from the input/output pad, and
a second input buffer configured to be driven by a third voltage to receive input data of a high-frequency band from the input/output pad.

6. The interface circuit of claim 5 , wherein the first voltage and the second voltage have a same voltage level.

7. The interface circuit of claim 5 , wherein a level of the third voltage is a same as a high level of the logic signal.

8. The transmitter circuit of claim 4 , wherein the main-driver circuit comprises:
a PMOS transistor configured to pull up a voltage of the input/output pad to the second voltage by the first signal;
a first resistor connected between the PMOS transistor and the input/output pad;
an NMOS transistor configured to pull down the voltage of the input/output pad to a third voltage by the first signal; and
a second resistor connected between the NMOS transistor and the input/output pad.

9. The transmitter circuit of claim 4 , wherein the main-driver circuit comprises:
a first NMOS transistor configured to pull up a voltage of the input/output pad to the second voltage by the first signal;
a first resistor connected between the first NMOS transistor and the input/output pad;
an inverter configured to generate an inverted signal by inverting the first signal;
a second NMOS transistor configured to pull down the voltage of the input/output pad to a third voltage by the inverted signal; and
a second resistor connected between the second NMOS transistor and the input/output pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Koo Kyunghoi
• Park Sanghune
• Choi Jin-Ho

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K19/018528

  with at least one differential stage · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K19/017518

  using a combination of bipolar and field effect transistors [BIFET] · CPC title