Memory cells having a folded digit line architecture

Patent metadata

Field	Value
Publication number	US-9653468-B2
Application number	US-201615207169-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Nov 4, 2009
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.

First claim

What is claimed is:

1. An apparatus comprising:
first and second semiconductor active regions;
a first trench formed in the first semiconductor active region to define first and second legs, wherein the first and second legs sandwich the first trench therebetween;
a second trench formed in the second semiconductor active region to define third and fourth legs, wherein the third and fourth legs sandwich the second trench therebetween;
first conductive line in electrical contact with the first leg, wherein the first conductive line is elongated to pass through over the second trench with an electrical isolation from each of the third and fourth legs; and
a second conductive line in electrical contact with the third leg, wherein the second conductive line is elongated to pass through over the first trench with an electrical isolation from each of the first and second legs.

2. The apparatus according to claim 1 , wherein the first and second conductive lines are elongated in substantially parallel to each other.

3. The apparatus according to claim 1 ,
wherein the first and second semiconductor active regions are arranged in a first direction;
wherein the first and second legs are arranged in a second direction crossing the first direction;
wherein the third and fourth legs are arrange in the second direction; and
wherein each of the first and second conductive lines is elongated in a first direction.

4. The apparatus according to claim 3 , wherein the first direction is substantially orthogonal to the second direction so that each of the first and second conductive lines is elongated substantially perpendicularly to the second direction.

5. The apparatus according to claim 4 , wherein the first semiconductor active region is shifted in position in the second direction with respect to the second semiconductor active region such that each of the first and second conductive lines is elongated straightly in the first direction.

6. The apparatus according to claim 1 , further comprising first and second storage devices;
wherein the first storage device is in an electrical contact with the second leg;
wherein the second storage device is in an electrical contact with the fourth leg;
wherein the first conductive line runs between the second storage device and the second conductive line; and
wherein the second conductive line runs between the first storage device and the first conductive line.

7. The apparatus according to claim 6 , wherein each of the first and second storage devises comprises a capacitor.

8. The apparatus according to claim 1 ,
wherein each of the first and second semiconductor active regions is surrounded by a third trench; and
wherein the third trench is deeper than each of the first and second trenches.

9. An apparatus comprising:
a first memory cell access transistor including first and second source/drain regions and a first channel region therebetween;
a second memory cell access transistor including third and fourth source/drain regions and a second channel region therebetween;
a first word line extending to control the first channel region of the first memory cell access transistor;
a second word line extending to control the second channel region of the second memory cell access transistor;
a first digit line in electrical contact with the first source/drain region of the first memory cell access transistor, the first digit line extending over the second channel region and between the third and fourth source/drain regions of the second memory cell access transistor; and
a second digit line in electrical contact with the third source/drain region of the second memory cell, the second digit line extending over the first channel region and between the first and second source/drain regions of the first memory cell access transistor.

10. The apparatus according to claim 9 , further comprising first and second storage devices;
wherein the first storage device is in an electrical contact with the second source/drain region;
wherein the second storage device is in an electrical contact with the fourth source/drain region;
wherein the first digit line runs between the second conductive line and the second storage device; and
wherein the second digit line runs between the first conductive line and the first storage device.

11. The apparatus according to claim 10 , wherein each of the first and second storage devices comprises a capacitor.

12. The apparatus according to claim 9 ,
wherein the first and second memory cell access transistors are disposed in a first direction;
wherein the first and second source/drain regions are disposed in a second direction crossing the first direction;
wherein the third and fourth source/drain regions are disposed in the second direction;
wherein each of the first and second word lines extends in the second direction; and
wherein the each of the first and second digit lines extends in the first direction.

13. The apparatus according to claim 12 ,
wherein the first and second channel regions includes first and second center portions, respectively; and
wherein the first memory cell access transistor is shifted in position in the second direction with respect to the second memory cell access transistor such that the first conductive line extends over the second center portion of the second channel region and that the second conductive line extends over the first center portion of the first channel region.

14. The apparatus according to claim 9 , further comprising first and second capacitors that are in an electrical contact with the second and fourth source/drain regions, respectively.

15. An apparatus comprising:
a plurality of finFETs arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of finFETs comprises a first leg, a second leg, and a shallow trench formed therebetween;
a plurality of word lines, wherein each of the plurality of word lines is elongated along ones of the plurality of finFETs in an associated one of the plurality of rows; and
a plurality of first digit lines, wherein each of the plurality of first digit lines is elongated so as to have an electrical contact with the first leg of each of even-numbered ones of the finFETs in an associated one of the plurality of columns and pass through over the shallow trench of each of odd-numbered ones of the plurality of finFETs in the associated one of the plurality of columns with an electrical isolation from each of the first and second legs of each of the odd-numbered ones of the plurality of finFETs in the associated one of the plurality of columns.

16. The apparatus according to claim 15 , further comprising a plurality of second digit lines:
wherein each of the plurality of second digit lines is elongated so as to have an electrical contact with the first leg of each of odd-numbered ones of the finFETs in a corresponding one of the plurality of columns and pass through over the shallow trench of each of even-numbered ones of the plurality of finFETs in the corresponding one of the plurality of columns with an electrical isolation from each of the first and second legs of each of the even-numbered ones of the plurality of finFETs in the corresponding one of the plurality of columns; and
wherein the plurality of first digit lines and the plurality of second digit lines are arranged alternately.

17. The apparatus according to claim 16 , wherein each of the plurality of finFETs in each of odd-numbered ones of the plurality of rows is shifted in a row direction with respect to each of the plur

Assignees

• Micron Technology Inc

Inventors

• Tomishima Shigeki

Classifications

• H01L27/10808

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/10826 Primary

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic