Semiconductor device and method of making the same

Patent metadata

Field	Value
Publication number	US-9202921-B2
Application number	US-74953210-A
Country	US
Kind code	B2
Filing date	Mar 30, 2010
Priority date	Mar 30, 2010
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual channel transistor further includes a gate trench recessed into the semiconductor island and extending along the second direction. A gate is located in the gate trench. A first U-shaped channel region is formed in the semiconductor island. A second U-shaped channel region is formed in the semiconductor island, wherein the second U-shaped channel region is segregate from the first U-shaped channel region by the gate. During operation, the gate controls two U-shaped channel regions simultaneously.

First claim

What is claimed is:

1. A semiconductor device having a dual channel transistor, comprising:
a semiconductor island isolated by at least a first shallow trench isolation extending along a first direction and a second shallow trench isolation extending along a second direction, wherein the first shallow trench isolation intersects the second shallow trench isolation;
a gate trench extending along the second direction and recessed into the semiconductor island;
a gate extending along the second direction and disposed at the gate trench;
a first dielectric layer encapsulating the gate in the gate trench;
a first source/drain regions disposed along the second direction and disposed with respect to a top surface of the semiconductor island;
a second dielectric layer whose bottom is higher than that of the gate trench, embedded in the semiconductor island and disposed between the first source/drain regions;
a first U-shaped channel region disposed around the second dielectric layer and between the first source/drain regions;
a second source/drain regions disposed along the second direction and disposed with respect to the top surface of the semiconductor island;
a third dielectric layer embedded in the semiconductor island and between the second source/drain regions; and
a second U-shaped channel region disposed around the third dielectric layer and between the second source/drain regions.

2. The semiconductor device of claim 1 , wherein the first source/drain regions and the second source/regions are disposed at opposite sides of the semiconductor island.

3. The memory device of claim 1 , wherein the first source/drain regions and the second source/regions are disposed at opposite sides of the gate.

4. The semiconductor device of claim 1 , wherein the first source/drain regions are disposed in the semiconductor island.

5. The semiconductor device of claim 4 , further comprising a first conductive layer disposed on the first source/drain regions.

6. The semiconductor device of claim 5 , wherein the first conductive layer is also disposed in the gate trench and on the first dielectric layer.

7. The semiconductor device of claim 1 , wherein the second source/drain regions are disposed in the semiconductor island.

8. The semiconductor device of claim 7 , further comprising a second conductive layer disposed on the second source/drain regions.

9. The semiconductor device of claim 8 , wherein the second conductive layer is also disposed in the gate trench and on the first dielectric layer.

10. The semiconductor device of claim 1 , wherein the first source/drain regions and the second source/drain regions are symmetric with respect to the gate.

11. The semiconductor device of claim 1 , further comprising a source line coupling a first source in the first source/drain regions to a second source of the second source/drain regions.

12. The semiconductor device of claim 1 , further comprising a drain contact coupling a first drain in the first source/drain regions to a second drain in the second source/drain regions.

13. The semiconductor device of claim 1 , wherein a top surface of the first dielectric layer is lower than the top surface of the semiconductor island.

14. The semiconductor device of claim 1 , wherein the semiconductor island comprises a top portion and a bottom portion, such that the first U-shaped channel region and the second U-shaped channel region are disposed within the top portion and the bottom portion serves as an electric reservoir of the first U-shaped channel region and the second U-shaped channel region.

15. The semiconductor device of claim 1 , further comprising a periphery circuitry comprising at least a periphery gate comprising at least one layer.

16. The semiconductor device of claim 15 , further comprising a source line coupling a first source in the first source/drain regions to a second source of the second source/drain regions, wherein the source line comprises at least one layer that is substantially identical to the peripheral gate.

17. The semiconductor device of claim 1 , further comprising a spacer disposed on the semiconductor island and the spacer does not contact the gate.

18. A semiconductor device, comprising:
a semiconductor island isolated by a first shallow trench isolation extending along a first direction and a second shallow trench isolation extending along a second direction, wherein the first shallow trench isolation intersects the second shallow trench isolation;
a gate trench recessed into the semiconductor island and extending along the second direction;
a gate whose top surface is lower than that of the semiconductor island and embedded in the gate trench;
a first U-shaped channel region in the semiconductor island; and
a second U-shaped channel region in the semiconductor island, wherein the second U-shaped channel region is separated from the first U-shaped channel region by the gate.

19. The semiconductor device of claim 18 , further comprising a spacer disposed on the semiconductor island and the spacer does not contact the gate.

20. A semiconductor device, comprising:
a substrate including a plurality of first shallow trench isolations arranged along a first direction and a plurality of second shallow trench isolations arranged along a second direction, wherein the plurality of first shallow trench isolations and the plurality of second shallow trench isolations intersect and define a plurality of semiconductor islands;
a plurality of transistors, each of the transistor disposed in a corresponding semiconductor island, wherein each of the transistor comprises: a gate embedded in the semiconductor island and extending along a second direction; a first source/drain regions comprising a first source and a first drain and disposed along the second direction and disposed with respect to a top surface of the semiconductor island; a first U-shaped channel region disposed between the first source/drain regions; a second source/drain regions disposed along the second direction and disposed with respect to the top surface of the semiconductor island; a second U-shaped channel region disposed between the second source/drain regions; and
a plurality of source lines extending in the first direction intersecting the second direction, each of the source lines being coupled to a first source of the first source/drain region and a second source of the second source/drain regions.

21. The semiconductor device of claim 20 , further comprising: a peripheral circuitry disposed at a periphery region of the substrate, wherein the peripheral circuitry comprising at least a periphery gate comprising at least one layer.

22. The semiconductor device of claim 21 , wherein the source line comprises at least one layer that is substantially identical to the peripheral gate.

23. The semiconductor device of claim 20 , wherein each of the transistors further comprises a spacer disposed on the semiconductor island and the spacer does not contact the gate.

Assignees

• Wu Tieh-Chiang
• Nanya Technology Corp

Inventors

• Wu Tieh-Chiang

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6211 Primary

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H01L29/7851 Primary

  Electricity · mapped topic

• H01L27/10894

  Electricity · mapped topic

• H01L27/10879

  Electricity · mapped topic