Semiconductor devices having stacked structures and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9653430-B2
Application number	US-201514955124-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 1, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon,
wherein the first semiconductor chip comprises:
a first semiconductor substrate including a first through-electrode;
a first circuit layer on a front surface of the first semiconductor substrate; and
a first front pad in the first circuit layer and is electrically connected to the first through-electrode,

wherein the second semiconductor chip comprises:
a second semiconductor substrate including a second through-electrode;
a second circuit layer on a front surface of the second semiconductor substrate; and
a second front pad in the second circuit layer and is electrically connected to the second through-electrode,

wherein the front surface of the first semiconductor substrate faces the front surface of the second semiconductor substrate, and
wherein the first circuit layer directly contacts the second circuit layer such that the first semiconductor chip is bonded to the second semiconductor chip.

2. The device of claim 1 , wherein
the first semiconductor chip further comprises at least one first test pad that is electrically connected to the first through-electrode and is configured to electrically test the first semiconductor chip, and
the second semiconductor chip further comprises at least one second test pad that is electrically connected to the second through-electrode and is configured to electrically test the second semiconductor chip.

3. The device of claim 1 , wherein
the first circuit layer comprises a first upper insulating layer whose surface is coplanar with a surface of the first front pad, wherein the first upper insulating layer is configured to inhibit a constituent of the first front pad from being diffused, and
the second circuit layer comprises a second upper insulating layer whose surface is coplanar with a surface of the second front pad, wherein the second upper insulating layer is configured to inhibit a constituent of the second front pad from being diffused,
wherein the surface of the first upper insulating layer directly contacts the surface of the second upper insulating layer.

4. The device of claim 3 , wherein
the first circuit layer further comprises a first interlayer dielectric layer between the first semiconductor substrate and the first upper insulating layer to cover a first integrated circuit on the first semiconductor substrate, and
the second circuit layer further comprises a second interlayer dielectric layer between the second semiconductor substrate and the second upper insulating layer to cover a second integrated circuit on the second semiconductor substrate.

5. The device of claim 1 , wherein the first and second front pads directly contact each other such that the first and second through-electrodes are electrically connected to each other.

6. The device of claim 1 , wherein
the first semiconductor chip further comprises a first backside pad on a backside surface of the first semiconductor substrate electrically connected to the first through-electrode, and
the second semiconductor chip further comprises a second backside pad on a backside surface of the second semiconductor substrate electrically connected to the second through-electrode.

7. The device of claim 6 , wherein at least one of the first and second semiconductor chips further comprises a backside insulating layer on the backside surface of the corresponding semiconductor substrate,
wherein the backside insulating layer includes a surface coplanar with a surface of corresponding backside pad.

8. The device of claim 6 , further comprising an interconnection terminal coupled to at least one of the first and second backside pads.

9. A semiconductor device comprising:
a first single block comprising two first semiconductor chips that are stacked one atop the other and having a first face-to-face structure in which front surfaces of the first semiconductor chips face each other; and
a second single block, which is stacked on the first single block, comprising two second semiconductor chips that are stacked one atop the other and having a second face-to-face structure in which front surfaces of the second semiconductor chips face each other,
wherein each of the first semiconductor chips comprises:
a first semiconductor substrate having a first top surface on which a first circuit layer is provided and a first bottom surface opposite the first top surface;
a first through-electrode penetrating the first semiconductor substrate and electrically connected to the first circuit layer;
a first front pad in the first circuit layer and electrically connected to the first through-electrode;
a first interlayer dielectric layer on the first top surface of the first semiconductor substrate to cover the first circuit layer; and
a first upper insulating layer on the first interlayer dielectric layer configured to inhibit a constituent of the first front pad from being diffused,
wherein the first front surfaces of the first semiconductor substrates included in the first single block face each other to constitute the first face-to-face structure such that the first upper insulating layers and the first front pads of the first semiconductor chips respectively face each other.

10. The device of claim 9 , wherein each of the second semiconductor chips comprises:
a second semiconductor substrate having a second top surface on which a second circuit layer is provided and a second bottom surface opposite the second top surface;
a second through-electrode penetrating the second semiconductor substrate and electrically connected to the second circuit layer;
a second front pad in the second circuit layer and electrically connected to the second through-electrode;
a second interlayer dielectric layer on the second top surface of the second semiconductor substrate to cover the second circuit layer; and
a second upper insulating layer on the second interlayer dielectric layer configured to inhibit a constituent of the second front pad from being diffused,
wherein the second front surfaces of the second semiconductor substrates included in the second single block face each other to constitute the second face-to-face structure such that the second upper insulating layers and the second front pads of the second semiconductor chips respectively face each other.

11. The device of claim 10 , wherein
the first semiconductor chips respectively further comprise first backside pads on the first bottom surfaces of corresponding first semiconductor substrates and electrically connected to corresponding first through-electrodes, and
the second semiconductor chips respectively further comprise second backside pads on the second bottom surfaces of corresponding second semiconductor substrates and electrically connected to corresponding second through-electrodes.

12. The device of claim 11 , wherein the first and second single blocks are bonded to each other to have a back-to-back structure in which the first backside pad of the first semiconductor chip included in one of the first and second single blocks faces the second backside pad of the second semiconductor chip included in the other of the first and second single blocks.

13. The device of claim 12 , further comprising at least one interconnection terminal between the first and second single blocks to electrically connect the first backside pad of the first semiconductor chip to the second backside pad of the second semiconductor chip,
wherein the first single block is spaced from the second single block by the interconne

Assignees

• Kim Taeyeong
• Park Byung Lyul
• Kim Seokho
• Kang Pil-Kyu
• Kim Hyoju
• An Jin Ho
• Jang Joo Hee
• Samsung Electronics Co Ltd

Inventors

• Kim Taeyeong
• Park Byung Lyul
• Kim Seokho
• Kang Pil-Kyu
• Kim Hyoju
• An Jin Ho
• Jang Joo Hee

Classifications

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title