Signal processing system and integrated circuit comprising a prefetch module and method therefor

Patent metadata

Field	Value
Publication number	US-9652413-B2
Application number	US-200913382796-A
Country	US
Kind code	B2
Filing date	Jul 20, 2009
Priority date	Jul 20, 2009
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates.

First claim

The invention claimed is:

1. A processing system comprising:
a memory;
a master device to issue a request to access information at the memory, the request including an access address;
a programmable control register to define a first range of memory addresses and first parameters that define whether prefetching is enabled for accesses to addresses within the first range of memory addresses, a second range of memory addresses and second parameters that define whether prefetching is enabled for accesses to addresses within the second range of memory addresses, and default settings that define whether prefetching is enabled for accesses to addresses that are not within the first or the second range of memory addresses; and
a prefetch module to determine whether prefetching of information relative to the access address is enabled based on the first parameters in response to determining that the access address is included in the first range of memory addresses, to determine whether prefetching of information relative to the access address is enabled based on the second parameters in response to determining that the access address is included in the second range of memory addresses, and to determine whether prefetching of information relative to the access address is enabled based on the default settings in response to determining that the access address is not included within the first range of memory addresses or within the second range of memory addresses.

2. The processing system of claim 1 , wherein the programmable control register further defines a parameter specifying that the first range of memory addresses is associated with data structures, and if the access address falls within the first range of memory addresses, the prefetch module is arranged to enable prefetching if the request is a data request.

3. The processing system of claim 2 , wherein the prefetch module is arranged to disable prefetching if the request is an instruction request.

4. The processing system of claim 1 , wherein:
the programmable control register further defines a parameter specifying whether burst prefetching is enabled for accesses to addresses within the first range of memory addresses if the request is a burst request.

5. The processing system of claim 1 , wherein the programmable control register further defines a parameter specifying that the first range of addresses is associated with program code, and if the access address falls within the first range of memory addresses, the prefetch module is arranged to enable prefetching if the request is an instruction request.

6. The processing system of claim 5 , wherein the prefetch module is arranged to disable prefetching if the request is a data request.

7. The processing system of claim 5 , wherein the programmable control register further defines a parameter specifying that burst prefetching is enabled for accesses to addresses within the first range of memory addresses, and the prefetch module is arranged to enable prefetching if the request is a data burst request.

8. The processing system of claim 1 , wherein the prefetch module is further arranged to configure a number of buffer lines to prefetch based on an attribute of the request.

9. The processing system of claim 1 , wherein the prefetch module is arranged to determine whether prefetching is permitted for requests from the master device, and to disable prefetching if prefetching is not permitted.

10. A method comprising:
defining, at a programmable control register, a first range of memory addresses and first parameters that define whether prefetching is enabled for accesses to addresses within the first range of memory addresses, a second range of memory addresses and second parameters that define whether prefetching is enabled for accesses to addresses within the second range of memory addresses, and default settings that define whether prefetching is enabled for accesses to addresses that are not within the first or the second range of memory addresses;
receiving a request to access information from a memory, the request from a master device and including an access address;
receiving the access address at a prefetch module; and
determining, at the prefetch module, whether prefetching of information relative to the access address is enabled based on the first parameters in response to determining that the access address is included in the first range of memory addresses, determining whether prefetching of information relative to the access address is enabled based on the second parameters in response to determining that the access address is included in the second range of memory addresses, and determining whether prefetching of information relative to the access address is enabled based on the default settings in response to determining the access address is not included within the first range of memory addresses or within the second range of memory addresses.

11. The method of claim 10 , wherein the first range of memory addresses is associated with data structures, and if the access address falls within the first range of memory addresses, enabling prefetching if the request is a data request.

12. The method of claim 11 , further comprising disabling prefetching if the request is an instruction request.

13. The method of claim 10 , wherein the first range of memory addresses is associated with program code, and if the access address falls within the first range of memory addresses, enabling prefetching if the request is an instruction request.

14. The method of claim 13 , further comprising disabling prefetching if the request is a data request.

15. The method of claim 13 , wherein the programmable control register further defines a parameter specifying that burst prefetching is enabled for accesses to addresses within the first range of memory addresses, enabling prefetching if the request is a data burst request.

16. The method of claim 10 , further comprising determining whether prefetching is permitted for requests from the master device, and disabling prefetching if prefetching is not permitted.

17. The method of claim 10 , wherein the programmable control register further defines a second range of memory addresses, and if the access address does not fall within the first or within the second range of memory addresses, determining whether prefetching is enabled in accordance with the default settings.

18. A device comprising:
a programmable control register to store information identifying a first range of memory addresses, a second range of memory addresses, parameters that define whether prefetching is enabled for accesses to addresses within the first and second range of memory addresses, and default settings; and
a prefetch module to:
receive a request to access information from a memory, the request from a master device and including an access address; and
determining whether prefetching of information relative to the access address is enabled in response to determining the access address is included in the first range of memory addresses or is included in the second range of memory addresses;
wherein if the access address does not fall within the first range of memory addresses, within the second range of memory addresses, or within another identified range of memory addresses, determining whether prefetching is enabled in accordance with the default settings.

19. The device of claim 18 , wherein:
the first range of memory addresses is associated with data structures, and if the access address falls within the first range of

Assignees

• Robertson Alistair
• Circello Joseph
• Maiolani Mark
• Nxp Usa Inc

Inventors

• Robertson Alistair
• Circello Joseph
• Maiolani Mark

Classifications

• G06F12/0862

  with prefetch · CPC title

• G06F13/1631 Primary

  through address comparison · CPC title