Instruction and logic for non-blocking register reclamation

Patent metadata

Field	Value
Publication number	US-9652236-B2
Application number	US-201314139263-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

First claim

What is claimed is:

1. A processor, comprising circuitry to:
execute a first instruction and a second instruction, the first instruction ordered before the second instruction, the first instruction including a reference to a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register;
determine whether the second instruction is data-independent of the first instruction;
reassign the second physical register to another logical register before retirement of the first instruction based upon the determination whether the second instruction is data-independent of the first instruction;
execute one or more checkpoint instructions including references to one or more checkpoint logical registers assigned to one or more checkpoint physical registers, the checkpoint instructions ordered before the first instruction; and
determine whether the second physical register is unequal to each of the checkpoint physical registers;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the determination whether the second physical register is unequal to each of the checkpoint physical registers.

2. The processor of claim 1 , further comprising circuitry to:
identify latent execution of the first instruction, wherein latent execution includes expected latency above a threshold;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the identification of latent execution of the first instruction.

3. The processor of claim 1 , further comprising circuitry to:
execute a third instruction, the third instruction:
ordered after the first instruction;
including a reference to a third logical register assigned to a third physical register; and
data-dependent upon the first register; and

reassign the third physical register to another logical register after retirement of the first instruction based upon data-dependence upon the first register.

4. The processor of claim 1 , further comprising circuitry to:
determine whether the second physical register is a source of information to the first instruction;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the determination whether the second physical register is a source of information to the first instruction.

5. The processor of claim 1 , further comprising circuitry to:
determine an available number of physical registers below a threshold;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the determination of the available number of physical registers below a threshold.

6. A method comprising, within a processor:
executing a first instruction and a second instruction, the first instruction ordered before the second instruction, the first instruction including a reference a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register;
determining whether the second instruction is data-independent of the first instruction;
reassigning the second physical register to another logical register before retirement of the first instruction based upon determining whether the second instruction is data-independent of the first instruction;
executing one or more checkpoint instructions including references to one or more checkpoint logical registers assigned to one or more checkpoint physical registers, the checkpoint instructions ordered before the first instruction; and
determining whether the second physical register is unequal to each of the checkpoint physical registers;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon determining whether the second physical register is unequal to each of the checkpoint physical registers.

7. The method of claim 6 further comprising:
identifying latent execution of the first instruction, wherein latent execution includes expected latency above a threshold;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon identifying latent execution of the first instruction.

8. The method of claim 6 , further comprising:
executing a third instruction that is:
ordered after the first instruction;
includes a reference to a third logical register assigned to a third physical register; and
data-dependent upon the first register; and

reassigning the third physical register to another logical register after retirement of the first instruction based upon data-dependence upon the first register.

9. The method of claim 6 , further comprising:
determining whether the second physical register is a source of information to the first instruction;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the determining whether the second physical register is a source of information to the first instruction.

10. The method of claim 6 , further comprising:
determining an available number of physical registers below a threshold;
wherein the reassigning the second physical register to another logical register before retirement of the first instruction is based upon determining an available number of physical registers below the threshold.

11. A system comprising:
an interface to receive a first instruction and a second instruction;
a processor, including circuitry to:
execute the first instruction and the second instruction, the first instruction ordered before the second instruction, the first instruction including a reference a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register;
determine whether the second instruction is data-independent of the first instruction; and
reassign the second physical register to another logical register before retirement of the first instruction based upon the determination whether the second instruction is data-independent of the first instruction;
execute one or more checkpoint instructions including references to one or more checkpoint logical registers assigned to one or more checkpoint physical registers, the checkpoint instructions ordered before the first instruction; and
determine whether the second physical register is unequal to each of the checkpoint physical registers;
wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the determination whether the second physical register is unequal to each of the checkpoint physical registers.

12. The system of claim 11 , wherein:
the processor further includes circuitry to identify latent execution of the first instruction, wherein latent execution includes expected latency above a threshold; and
reassigning the second physical register to another logical register before retirement of the first instruction is based upon the identification of latent execution of the first instruction.

13. The system of claim 11 , wherein the processor further includes circuitry to:
execute a third instruction, the third instruction:
ordered after the first instruction;
including a reference to a third logical register a

Assignees

• Srinivasan Srikanth T
• Dechene Mark J
• Ilin Yury N
• Deinlein Justin M
• Wang Christine E
• Merten Matthew C
• Intel Corp

Inventors

• Srinivasan Srikanth T
• Dechene Mark J
• Ilin Yury N
• Deinlein Justin M
• Wang Christine E
• Merten Matthew C

Classifications

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/30109 Primary

  having multiple operands in a single register · CPC title