Systems and methods to predict load data values
US-10761844-B2 · Sep 1, 2020 · US
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Dechene Mark J patents
Dechene Mark J is listed as an inventor on 8 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Dechene Mark J |
| Total patents | 8 |
| First publication | Nov 15, 2016 |
| Latest publication | Sep 1, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods to predict load data values
US-2020004536-A1 · Jan 2, 2020 · US
Processor prefetch throttling based on short streams
US-10379864-B2 · Aug 13, 2019 · US
Supporting binary translation alias detection in an out-of-order processor
US-10228956-B2 · Mar 12, 2019 · US
Processor prefetch throttling based on short streams
US-2018181402-A1 · Jun 28, 2018 · US
Supporting binary translation alias detection in an out-of-order processor
US-2018095765-A1 · Apr 5, 2018 · US
Instruction and logic for non-blocking register reclamation
US-9652236-B2 · May 16, 2017 · US
Two level re-order buffer
US-9495159-B2 · Nov 15, 2016 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 8 |
| Srinivasan Srikanth T | 1 |
| Dechene Mark J | 1 |
| Ilin Yury N | 1 |
| Deinlein Justin M | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30145 | 6 |
| G06F9/3832 | 4 |
| G06F9/30043 | 4 |
| G06F9/3838 | 4 |
| G06F8/445 | 3 |