Dummy FinFET structure and method of making same

Patent metadata

Field	Value
Publication number	US-9647066-B2
Application number	US-201213454960-A
Country	US
Kind code	B2
Filing date	Apr 24, 2012
Priority date	Apr 24, 2012
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active FinFET over a substrate, wherein the active FinFET comprises active semiconductor fins and an active gate structure over all of the active semiconductor fins, a first active semiconductor fin of the active semiconductor fins having a first longitudinal axis, each of the active semiconductor fins being perpendicular to the active gate structure and having a topmost surface that is co-planar with the topmost surface of each other active semiconductor fin, the active gate structure comprising at least one contact portion, and the active FinFET having four sides;
a first dummy FinFET over the substrate, wherein the first dummy FinFET comprises a first plurality of dummy semiconductor fins, each dummy semiconductor fin of the first plurality of dummy semiconductor fins having a rectangular shape in a top-down view, being perpendicular to each of the active semiconductor fins, and having a topmost surface co-planar with the topmost surface of each of the active semiconductor fins, and wherein the first dummy FinFET further comprises a first dummy gate structure over all of the first plurality of dummy semiconductor fins, the first dummy gate structure being perpendicular to the active gate structure, the first dummy FinFET laterally adjacent a first side of the active FinFET, the first longitudinal axis intersecting at least one fin of the first plurality of dummy semiconductor fins;
a second dummy FinFET over the substrate, wherein the second dummy FinFET comprises a second plurality of dummy semiconductor fins, each dummy semiconductor fin of the second plurality of dummy semiconductor fins having a rectangular shape in the top-down view and being perpendicular to each of the first plurality of dummy semiconductor fins, and wherein the second dummy FinFET further comprises a second dummy gate structure over all of the second plurality of dummy semiconductor fins, the second dummy FinFET laterally adjacent a second side of the active FinFET, the second side of the active FinFET being opposite the first side of the active FinFET, the first longitudinal axis intersecting at least one fin of the second plurality of dummy semiconductor fins;
a third dummy FinFET over the substrate, wherein the third dummy FinFET comprises a third plurality of dummy semiconductor fins, the third dummy FinFET laterally adjacent a third side of the active FinFET;
a fourth dummy FinFET over the substrate, wherein the fourth dummy FinFET comprises a fourth plurality of dummy semiconductor fins, the fourth dummy FinFET laterally adjacent a fourth side of the active FinFET, the fourth side of the active FinFET being opposite the third side of the active FinFET, each of the first, the second, the third, and the fourth dummy FinFETs being laterally separated from the active gate structure including the at least one contact portion, and no one active or dummy FinFET sharing a common gate structure with another active or dummy FinFET;
a dielectric layer formed between each of the active semiconductor fins and each of the first, the second, the third, and the fourth plurality of dummy semiconductor fins, wherein the topmost surfaces of the active semiconductor fins, the first plurality of dummy semiconductor fins, and the second plurality of dummy semiconductor fins are higher than a topmost surface of the dielectric layer; and
a further plurality of dummy fins formed to surround a space around the active FinFET, the space being defined by a spacing from the active FinFET on the first side, the second side, the third side, and at least partially on the fourth side of the active FinFET.

2. The semiconductor device of claim 1 , wherein the active semiconductor fins are parallel to a plurality of dummy semiconductor fins of at least one of the first, the second, the third, and the fourth dummy FinFETs.

3. The semiconductor device of claim 1 further comprising:
the first active semiconductor fin having a first width;
a second active semiconductor fin, the second active semiconductor fin laterally spaced from the first active semiconductor fin by a first spacing; and
a second spacing comprising the first width and the first spacing, wherein the active FinFET is laterally spaced from the first dummy FinFET, the second dummy FinFET, the third dummy FinFET, and the fourth dummy FinFET by a third spacing, the third spacing being from one tenth of the second spacing to five times the second spacing.

4. The semiconductor device of claim 1 , wherein the active semiconductor fins have a same width and a same length as a plurality of dummy semiconductor fins.

5. The semiconductor device of claim 1 , comprising a plurality of dummy semiconductor fins that are longer and wider than the active semiconductor fins.

6. The semiconductor device of claim 1 , comprising a plurality of dummy semiconductor fins that are shorter and narrower than the active semiconductor fins.

7. A FinFET device comprising:
a first FinFET over a substrate, the first FinFET comprising a first plurality of semiconductor fins and an active gate structure over and perpendicular to the first plurality of semiconductor fins, one fin of the first plurality of semiconductor fins having a first longitudinal axis, the first plurality of semiconductor fins consisting of all semiconductor fins under the active gate structure, each of the first plurality of semiconductor fins being parallel to each other of the first plurality of semiconductor fins, and the first FinFET being an active FinFET;
a second FinFET over the substrate, the second FinFET comprising a second plurality of semiconductor fins and a first dummy gate structure over and perpendicular to the second plurality of semiconductor fins, each semiconductor fin of the second plurality of semiconductor fins having a rectangular shape in a top-down view, the second plurality of semiconductor fins consisting of all semiconductor fins under the first dummy gate structure, the second plurality of semiconductor fins being perpendicular to the first plurality of semiconductor fins, and the second FinFET being electrically isolated from all active devices, the second FinFET being nearer to a first side of the first FinFET than any other FinFET, the first longitudinal axis intersecting at least one fin of the second plurality of semiconductor fins; and
a third FinFET over the substrate, the third FinFET comprising a third plurality of semiconductor fins and a second dummy gate structure over and perpendicular to the third plurality of semiconductor fins, each semiconductor fin of the third plurality of semiconductor fins having a rectangular shape in a top-down view, the third plurality of semiconductor fins consisting of all semiconductor fins under the second dummy gate structure, the third plurality of semiconductor fins being perpendicular to the second plurality of semiconductor fins, and the third FinFET being electrically isolated from all active devices, the third FinFET being nearer to a second side of the first FinFET than any other FinFET, the second side of the first FinFET being opposite the first side of the first FinFET, the first longitudinal axis intersecting at least one fin of the third plurality of semiconductor fins,
wherein the second FinFET is aligned relative to the first FinFET such that a center axis of the first FinFET substantially bisects the second FinFET, the center axis being parallel to the first plurality of semiconductor fins and defined by a mid-line between an outer edge of a first outer fin of the first plurality of semiconductor fins and an outer edge of a second outer fin of the first plurality of semiconductor fins, the second outer fin being on an opposite side of the first FinFET than the first outer fin, and where

Assignees

• Lu Chang-Shen
• Peng Chih-Tang
• Huang Tai-Chun
• Jeng Pei-Ren
• Lien Hao-Ming
• Lin Yi-Hung
• Lee Tze-Liang
• Jang Syun-Ming
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chang-Shen
• Peng Chih-Tang
• Huang Tai-Chun
• Jeng Pei-Ren
• Lien Hao-Ming
• Lin Yi-Hung
• Lee Tze-Liang
• Jang Syun-Ming

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title

• H10D62/17 Primary

  Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title