Depression filling method and processing apparatus

Patent metadata

Field	Value
Publication number	US-9646879-B2
Application number	US-201414582243-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 27, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region.

First claim

What is claimed is:

1. A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate, the depression penetrating the insulating film so as to extend to the semiconductor substrate, the method comprising:
forming a first semiconductor layer doped with an impurity along a wall surface which defines the depression, the first semiconductor layer including a first amorphous semiconductor region which extends along a sidewall surface defining the depression;
forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer, the second semiconductor layer including a second amorphous semiconductor region formed on the first amorphous semiconductor region;
annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and
etching the first amorphous semiconductor region and the second amorphous semiconductor region,
wherein a sequence which includes forming a first semiconductor layer, forming a second semiconductor layer, annealing the workpiece, and etching the first amorphous semiconductor region and the second amorphous semiconductor region, is repeated.

2. The method of claim 1 , wherein the second semiconductor layer is an undoped semiconductor layer.

3. The method of claim 1 , further comprising:
forming a liner layer prior to forming the first semiconductor layer,
wherein the liner layer is an undoped semiconductor layer and includes a third amorphous semiconductor region along the sidewall surface, and
wherein the first semiconductor layer is formed on the liner layer.

4. The method of claim 3 , wherein the first semiconductor layer, the second semiconductor layer and the liner layer are made of silicon, and further comprising:
forming a seed layer with an aminosilane-based gas or a high-order silane gas prior to forming the liner layer,
wherein the seed layer is formed on the wall surface and the liner layer is formed on the seed layer.

Assignees

• Tokyo Electron Ltd

Inventors

• Kakimoto Akinobu
• Chiba Youichirou
• Yamada Takumi
• Suzuki Daisuke

Classifications

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P72/0434

  mainly by convection · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title