Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9640651-B2
Application number	US-201415116288-A
Country	US
Kind code	B2
Filing date	Oct 6, 2014
Priority date	Feb 10, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

First claim

The invention claimed is:

1. A semiconductor device that comprises a semiconductor substrate, the semiconductor device comprising:
a first region of an n-type provided in the semiconductor substrate and exposed on a surface of the semiconductor substrate;
a second region of a p-type provided below the first region;
a third region of the n-type provided below the second region and separated from the first region by the second region;
a plurality of gate trenches provided in the surface, penetrating the first region and the second region, and reaching the third region;
first insulating layers provided in the gate trenches;
gate electrodes provided in the gate trenches and facing the second region via the first insulating layers;
fourth regions of the p-type being in contact with lower ends of the gate trenches;
a termination trench provided in the surface and extending so as to surround a region in which the plurality of gate trenches is provided in a planar view of the surface;
a second insulating layer provided in the termination trench;
a p-type lower end region of the p-type being in contact with a lower end of the termination trench;
a p-type outer circumference region of the p-type provided on an outer circumferential side of the termination trench, being in contact with the termination trench, and exposed on the surface;
a plurality of guard ring regions of the p-type provided on the outer circumferential side of the p-type outer circumference region and exposed on the surface; and
an n-type outer circumference region of the n-type provided on the outer circumferential side of the termination trench, connected to the third region, separating the p-type outer circumference region from the guard ring regions, and separating the guard ring regions from each another,
wherein
a step portion is provided on the surface so that the surface comprises a first surface and a second surface projecting from the first surface,
the termination trench is provided in the second surface,
the p-type outer circumference region is exposed in a range extending across the second surface and the first surface, and
the plurality of guard ring regions is exposed on the first surface.

2. The semiconductor device of claim 1 , wherein an interval between the termination trench and the step portion is equal to or more than 10 μm.

3. The semiconductor device of claim 1 , wherein
the p-type outer circumference region includes:
an Al high density region located in a region at an outer circumferential side end portion of the p-type outer circumference region and exposed on the surface, and having a density of Al higher than a density of B, and
a B high density region bordering the Al high density region and having a density of B higher than a density of Al.

4. The semiconductor device of claim 3 , wherein a width of the Al high density region is wider than a width of each of the guard ring regions.

5. The semiconductor device of claim 1 , wherein
a part of the p-type lower end region extends in a range provided on an inner circumferential side of the termination trench, and
the part of the p-type lower end region extending in the range provided on the inner circumferential side of the termination trench does not extend to an upper side with respect to the lower end of the termination trench.

6. The semiconductor device of claim 1 , wherein the guard ring regions contain Al.

7. A method of manufacturing the semiconductor device of claim 1 , the method comprising steps of:
growing a p-type layer on an n-type layer;
removing a part of the p-type layer so as to form a surface on which the n-type layer is exposed and a surface on which the p-type layer is exposed and projecting from the surface on which the n-type layer is exposed;
implanting p-type impurities in a range extending across the surface on which the n-type layer is exposed and the surface on which the p-type layer is exposed so as to form the p-type outer circumference region;
implanting p-type impurities into the surface on which the n-type layer is exposed so as to form the guard ring regions; and
forming the termination trench in the surface on which the p-type layer is exposed.

Assignees

• Takaya Hidefumi
• Saito Jun
• Soeno Akitaka
• Hamada Kimimori
• Mizuno Shoji
• Aoi Sachiko
• Watanabe Yukihiko
• Toyota Motor Co Ltd
• Denso Corp

Inventors

• Takaya Hidefumi
• Saito Jun
• Soeno Akitaka
• Hamada Kimimori
• Mizuno Shoji
• Aoi Sachiko
• Watanabe Yukihiko

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H01L21/761

  Electricity · mapped topic