Self-aligned gate contact formation

Patent metadata

Field	Value
Publication number	US-9640625-B2
Application number	US-201414261823-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Apr 25, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

First claim

What is claimed is:

1. A method of forming a FinFET semiconductor device, the method comprising:
forming a set of gate structures over a substrate;
patterning a sacrificial layer to form a set of contact placeholders over a set of fins formed from the substrate;
forming a barrier layer over the set of contact placeholders;
depositing a fill material over the barrier layer;
etching through the barrier layer atop each of the set of contact placeholders;
etching a hard mask from the set of contact placeholders to expose the sacrificial layer;
removing the sacrificial layer of the contact placeholders;
removing an oxide over the set of fins to form the set of SD contact openings in the semiconductor device;
patterning a lithography masking structure over the semiconductor device to form the gate contact opening over the at least one of the set of gate structures;
forming a gate contact opening by etching an oxide over at least one of the set of gate structures;
removing, selective to a metal stack of the at least one of the set of gate structures, the barrier layer and an interlayer fill material within the gate contact opening;
removing the lithography masking structure from over the semiconductor device; forming a set of source/drain (S/D) contact openings in the semiconductor device by removing the sacrificial layer from atop the set of fins; and
depositing a metal material over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings.

2. The method according to claim 1 , the forming the barrier layer comprising:
forming a first nitride layer over the set of gate structures and the set of contact placeholders;
forming the interlayer fill material over the first nitride layer; and
forming a second nitride layer over the interlayer fill material.

3. The method according to claim 1 , wherein the sacrificial layer is removed using an anisotropic etch process with tetramethylammonium hydroxide (TMAH), and wherein the oxide over the set of fins is removed using Diluted Hydrofluoric acid (dHF).

4. The method according to claim 1 , further comprising
providing an oxide between each of the set of gates;
forming a first oxide layer over each of the set of gates and over the oxide between each of the set of gates, wherein the sacrificial layer is formed over the first oxide layer;
forming a second oxide layer over the sacrificial layer;
patterning the second oxide layer to form the set of contact placeholders; and
removing the first oxide layer and the second oxide layer remaining exposed following formation of the set of contact placeholders.

5. The method according to claim 1 , the set of contact placeholders comprising at least one of the following: amorphous-silicon, polysilicon, and oxide.

6. The method according to claim 1 , further comprising:
providing nitride over the set of contact placeholders to form a barrier layer;
depositing a fill material over the semiconductor device following the etching of the barrier layer from the set of contact placeholders, leaving a nitride spacer; and
patterning the fill material between the set of contact placeholders to form the gate contact opening, wherein a layer of nitride remains between the gate contact opening and the set of contact placeholders.

7. The method according to claim 6 , the forming the set of S/D contact openings comprising removing the sacrificial layer using an anisotropic etch process with tetramethylammonium hydroxide (TMAH).

8. A method for forming self-aligned contacts in a FinFET semiconductor device, the method comprising:
forming a set of gate structures over a substrate;
patterning a sacrificial layer to form a set of contact placeholders over a set of fins formed from the substrate;
forming the barrier layer over the set of contact placeholders;
depositing a fill material over the barrier layer;
etching through the barrier layer atop each of the set of contact placeholders;
etching a hard mask from the set of contact placeholders to expose the sacrificial layer;
removing the sacrificial layer of the contact placeholders;
forming a gate contact opening by etching an oxide over at least one of the set of gate structures;
removing an oxide over the set of fins to form the set of S/D contact openings in the semiconductor device;
forming a set of source/drain (S/D) contact openings in the semiconductor device by removing the sacrificial layer from atop the set of fins;
depositing a metal material over the semiconductor device to form a gate contact within the gate contact opening and a set of SD contacts within the set of SD contact openings;
patterning a lithography masking structure over the semiconductor device to form the gate contact opening over the at least one of the set of gate structures;
removing, selective to a metal stack of the at least one of the set of gate structures, the barrier layer and an interlayer fill material within the gate contact opening; and
removing the lithography masking structure from over the semiconductor device.

9. The method according to claim 8 , the forming the barrier layer comprising:
forming a first nitride layer over the set of gate strictures and the set of contact placeholders;
forming the interlayer fill material over the first layer of nitride; and
forming a second nitride layer over the interlayer fill material.

10. The method according to claim 9 , wherein the sacrificial layer is removed using an anisotropic etch process with tetramethylammonium hydroxide (TMAH), and wherein the oxide over the set of fins is removed using Diluted HydroFluoric acid (dHF).

11. The method according to claim 9 , further comprising
providing an oxide between each of the set of gates;
forming a first oxide layer over each of the set of gates and over the oxide between each of the set of gates, wherein the sacrificial layer is formed over the first oxide layer;
forming a second oxide layer over the sacrificial layer;
patterning the second oxide layer to form the set of contact placeholders; and
removing the first oxide layer and the second oxide layer remaining exposed following formation of the set of contact placeholders.

12. The method according to claim 8 , the set of contact placeholders comprising at least one of the following: amorphous-silicon, polysilicon, and oxide.

13. The method according to claim 8 , further comprising:
providing nitride over the set of contact placeholders to form a barrier layer;
depositing a fill material over the semiconductor device following the etching of the barrier layer from the set of contact placeholders, leaving a nitride spacer; and
patterning the fill material between the set of contact placeholders to form the gate contact opening, wherein a layer of nitride remains between the gate contact opening and the set of contact placeholders.

14. The method according to claim 13 , the forming the set of S/D contact openings comprising removing the sacrificial layer using an anisotropic etch process with tetramethylammonium hydroxide (TMAH).

Assignees

• Globalfoundries Inc

Inventors

• Bouche Guillaume
• Wei Andy Chih-Hung
• Wells Gabriel Padron
• Labonte Andre P
• Wan Jing

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/0698 Primary

  Local interconnections · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title