Serial capacitor device with middle electrode contact and methods of making same

Patent metadata

Field	Value
Publication number	US-9640608-B1
Application number	US-201615052961-A
Country	US
Kind code	B1
Filing date	Feb 25, 2016
Priority date	Feb 25, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.

First claim

What is claimed:

1. A method, comprising:
forming a bottom electrode embedded in a first dielectric layer;
forming a first recess in a second dielectric layer disposed above the first dielectric layer, the recess exposing at least a portion of the bottom electrode;
forming a lower dielectric layer above the bottom electrode;
forming a middle electrode in the recess above the lower dielectric layer and above a sidewall of the first recess;
forming an upper dielectric layer in the first recess above the middle electrode;
forming a third dielectric layer in the first recess;
forming a second recess in the third dielectric layer, the second recess including a via opening exposing a portion of the bottom electrode; and
forming a conductive material in the second recess to define a top electrode and to define a via coupling the top electrode to the bottom electrode.

2. The method of claim 1 , further comprising:
forming a fourth dielectric layer above the top electrode;
forming a first contact opening in the fourth dielectric layer exposing the top electrode;
forming a second contact opening in the fourth dielectric layer exposing an extension portion of the middle electrode disposed above the sidewall; and
forming a conductive material in the first and second contact openings.

3. The method of claim 1 , wherein forming the second recess comprises:
forming a patterned mask layer above the third dielectric layer, the patterned mask layer comprising a mask element disposed above the sidewall; and
etching the third dielectric layer in the presence of the mask element to define the second recess, wherein a remaining portion of the third dielectric layer defines an isolation region disposed above a portion of the extension region and laterally disposed between the extension region and the top electrode after the conductive material is formed in the second recess.

4. The method of claim 1 , further comprising:
forming a barrier layer above the first dielectric layer and the bottom electrode, wherein the first recess exposes a portion of the barrier layer disposed above the bottom electrode; and
forming the lower dielectric layer above the barrier layer.

5. The method of claim 1 , further comprising:
forming a barrier layer above the first dielectric layer and the bottom electrode, wherein the first recess exposes a portion of the barrier layer disposed above the bottom electrode; and
removing the exposed portion of the barrier layer prior to forming the lower dielectric layer.

6. The method of claim 1 , wherein a conductive region is formed in a logic region of the first dielectric layer, and the method further comprises:
forming a layer of conductive material in the recess above the bottom electrode and above a portion of the second dielectric layer;
forming a first patterned mask layer above the layer of conductive material;
etching the layer of conductive material to define the bottom electrode and a mask portion disposed above the second dielectric layer;
removing the first patterned mask layer;
forming the middle dielectric layer above the bottom electrode and the mask portion;
etching the first dielectric layer using the bottom electrode and the mask portion to define a third recess exposing the conductive feature; and
forming the conductive material in the third recess to define an interconnect structure contacting the conductive feature.

7. The method of claim 6 , further comprising:
forming a second patterned mask layer above the second dielectric layer, wherein the second patterned mask layer comprises a first via opening;
etching the second dielectric layer through the first via opening to define a second via opening in the second dielectric layer; and
etching the first dielectric layer using the bottom electrode and the mask portion to define a trench opening of the third recess and to extend the second via opening to expose the conductive feature.

8. The method of claim 7 , wherein the second patterned mask layer comprises a third via opening disposed above the bottom electrode, and the method further comprises:
etching the third dielectric layer through the third via opening to define a fourth via opening in the third dielectric layer;
forming a third patterned mask layer above the third dielectric layer, the patterned mask comprising a mask element disposed above the sidewall; and
etching the third dielectric layer in the presence of the mask element to define the second recess and to extend the fourth via opening through the third dielectric layer and the lower dielectric layer to expose the bottom electrode, wherein a remaining portion of the third dielectric layer defines an isolation region disposed above a portion of the extension region and laterally disposed between the extension region and the top electrode after the conductive material is formed in the second recess.

9. The method of claim 1 , wherein the middle electrode comprises at least one of TiN, Ti, TaN, or Ta.

10. The method of claim 9 , wherein forming the conductive material further comprises concurrently forming the conductive material in the second recess and the third recess.

11. The method of claim 9 , wherein the top electrode comprises copper.

Assignees

• Globalfoundries Inc

Inventors

• Lee Ki Young
• Cho Woong Lae
• Joung Jae Ho

Classifications

• H01L28/75

  Electricity · mapped topic

• H01L28/92 Primary

  Electricity · mapped topic

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title