Capacitive device

Patent metadata

Field	Value
Publication number	US-9362271-B2
Application number	US-201514822343-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Nov 27, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first conductive layer, a cap dielectric layer, and a first electrode. The well has a predetermined doping type. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench between the first and second shoulder portions. The first trench has sidewalls and a bottom surface. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer. The first electrode is in contact with the first shoulder portion and extends through the cap dielectric layer, the first conductive layer, and the first dielectric layer.

First claim

What is claimed is:

1. A capacitive device, comprising:
a substrate having a well structure buried therein, the well structure having a first predetermined doping type, the well comprising:
a first shoulder portion and a second shoulder portion, each having an upper surface;
a first trench, between the first and second shoulder portions, the first trench having sidewalls defining a trench width and a bottom surface defining a trench depth; and
a first stacked layer comprising a first dielectric layer on at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls and the bottom surface of the first trench, and a first conductive layer on the first dielectric layer;

a cap dielectric layer over the well and the first stacked layer; and
a first electrode in direct contact with the first shoulder portion wherein the first electrode extends through the cap dielectric layer and the first stacked layer.

2. The capacitive device of claim 1 , further comprising an isolation structure surrounding a portion of the first electrode, wherein the isolation structure electrically isolates the first electrode and the first conductive layer.

3. The capacitive device of claim 1 , wherein the substrate comprises a semiconductor material selected from the group consisting of silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP and combinations thereof.

4. The capacitive device of claim 1 , wherein the substrate is silicon, germanium or a compound semiconductor material.

5. The capacitive device of claim 1 , wherein the substrate exhibits a conductive characteristic of an intrinsic semiconductor material or a second predetermined doping type different from the first predetermined doping type.

6. The capacitive device of claim 5 , wherein the first predetermined doping type is a N-type doping and the second predetermined doping type is a P-type doping.

7. The capacitive device of claim 1 , further comprising:
a second stacked layer comprising a second dielectric layer and a second conductive layer, the second stacked layer on the first stacked layer; and
a second electrode in contact with the second conductive layer and extending through the cap dielectric layer, the second electrode being directly above one of the first shoulder portion or the second shoulder portion.

8. The capacitive device of claim 7 , wherein the second electrode is directly above the first shoulder portion, the first and second electrodes being aligned along the width of the trench.

9. The capacitive device of claim 7 , further comprising:
a third electrode in direct contact with the first conductive layer and extending through the cap dielectric layer, the second electrode being directly above the first shoulder portion, the first, second, and third electrodes being aligned along the width of the trench.

10. The capacitive device of claim 7 , wherein a distance between the first and second electrodes is less than a distance between the first and the third electrodes and less than a distance between the second and the third electrodes.

11. The capacitive device of claim 1 , wherein
the well further comprises:
a third shoulder portion having an upper surface; and
a second trench, between the second and third shoulder portions, having sidewalls defining a width of the second trench and a bottom surface defining a depth of the second trench;

the first dielectric layer lined along the upper surface of the third shoulder portion, the sidewalls of the second trench, and the bottom surface of the second trench; and
the capacitive device further comprises:
a second electrode in contact with the first conductive layer and extending through the cap dielectric layer, the second conductive layer being directly above the first shoulder portion, directly above the second shoulder portion, or directly above the third shoulder portion.

12. The capacitive device of claim 11 , wherein the first shoulder portion, the second shoulder portion or the third shoulder portion has a size sufficient to accommodate the first electrode.

13. A capacitive device, comprising:
a substrate having a well structure buried therein, the well structure having a first predetermined doping type different from a second predetermined doping type of the substrate, the well comprising:
M shoulder portions, M being a positive integer equal to or greater than 2, each shoulder portion of the M shoulder portions having an upper surface;
(M−1) trenches, an m-th trench of the (M−1) trenches being between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions, and the m-th trench of the (M−1) trenches having sidewalls and a bottom surface, m being a positive integer from 1 to (M−1); and
N sets of stacked layers lined along the upper surfaces of the M shoulder portions, the sidewalls of the (M−1) trenches, and the bottom surfaces of the (M−1) trenches, each set of the N sets of stacked layers comprising a dielectric layer and a conductive layer over the dielectric layer, N being a positive integer;

a cap dielectric layer over the well and the N sets of stacked layers; and
a first set of electrodes, at least one electrode of the first set of electrodes being variously in direct contact with the well, one or more other electrodes of the first set of electrodes being in direct contact with various conductive layers of the N sets of stacked layers, the first set of electrodes being aligned along a trench width direction and directly on or above a first one of the M shoulder portions.

14. The capacitive device of claim 13 , wherein
the conductive layers of the N sets of stacked layers each having a thickness equal to or greater than T a ;
the dielectric layers of the N sets of stacked layers each having a thickness equal to or greater than T b ; and
the (M−1) trenches each having a width equal to or greater than (2·N·(T a +T b )−T b ).

15. The capacitive device of claim 13 , wherein
the well and the conductive layers of each set of the N sets of stacked layers are configured to function as a capacitor having a first terminal and a second terminal;
the first set of electrodes comprise:
a first sub set of electrodes electrically coupled to the well or the conductive layer of a set of the N sets of stacked layers associated with the first terminal; and
a second sub set of electrodes electrically coupled to the well or the conductive layer of a set of the N sets of stacked layers associated with the second terminal.

16. The capacitive device of claim 13 , further comprising:
a second set of electrodes variously in contact with the well or conductive layers of the N sets of stacked layers, the second set of electrodes being aligned along the trench width direction and directly on or above a second shoulder portion of the M shoulder portions,
the second set of electrodes comprising:
a third sub set of electrodes electrically coupled to the well or the conductive layers of the N sets of stacked layers associated with the first terminal, the first sub set of electrode and the third sub set of electrodes being aligned along a trench width direction; and
a fourth sub set of electrodes electrically coupled to the well or the conductive layers of the N sets of stacked layers associated with the second terminal, the second sub set of electrode

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chou Chung-Yen
• Lin Po-Ken
• Tsai Chia-Shiung
• Lee Ru-Liang

Classifications

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title