Semiconductor packages

Patent metadata

Field	Value
Publication number	US-9640473-B2
Application number	US-201514811368-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Feb 24, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. The semiconductor package may include a semiconductor chip disposed in the cavity and coupled to chip connectors, the chip connectors of the semiconductor chip inserted into the connection window. The semiconductor package may include a dielectric layer filling the cavity and the connection window and configured to expose end portions of the chip connectors and to substantially cover the semiconductor chip. Related memory cards and related electronic systems are also provided.

First claim

What is claimed is:

1. A semiconductor package comprising:
an embedding substrate including a cavity opened at a first surface of the embedding substrate and including a connection window penetrating a bottom portion of the cavity opening a second surface of the embedding substrate, the second surface of the embedding substrate opposite to the first surface;
a first semiconductor chip disposed in the cavity and coupled to first chip connectors, the first chip connectors of the first semiconductor chip inserted into the connection window;
a dielectric layer filling the cavity and the connection window to expose end portions of the first chip connectors and covering the first semiconductor chip; and
a second semiconductor chip disposed on the second surface of the embedding substrate and coupled to second chip connectors, the second chip connectors of the second semiconductor chip connected to at least one of the first chip connectors,
wherein the cavity is configured to be recessed toward the second surface.

2. The semiconductor package of claim 1 , wherein the first chip connectors each have a vertical length greater than a thickness of the bottom portion of the cavity that the connection window penetrates.

3. The semiconductor package of claim 1 , further comprising a third semiconductor chip disposed on the second surface of the embedding substrate,
wherein the second and third semiconductor chips are located side by side without vertically overlapping with each other.

4. The semiconductor package of claim 3 ,
wherein the third semiconductor chip is coupled to third chip connectors, and
wherein at least one of the third chip connectors is connected to another one of the first chip connectors of the first semiconductor chip.

5. A semiconductor package comprising:
an embedding substrate including a cavity opened at a first surface of the embedding substrate and including a connection window penetrating a bottom portion of the cavity opening a second surface of the embedding substrate, the second surface of the embedding substrate opposite to the first surface, the cavity being configured to be recessed toward the second surface;
a first semiconductor chip disposed in the cavity and coupled to first chip connectors including a first connector and a second connector, the first connector and the second connector of the first chip connectors of the first semiconductor chip inserted into the connection window;
a dielectric layer filling the cavity and the connection window to expose end portions of the first and second connectors of the first chip connectors and covering the first semiconductor chip;
an external connector disposed on the dielectric layer;
a second semiconductor chip disposed on the second surface of the embedding substrate and coupled to a first connector of second chip connectors, the first connector of the second chip connectors of the second semiconductor chip connected to the first connector of the first chip connectors; and
a conductive connection structure electrically connecting a second connector of the second chip connectors to the external connector,
wherein the first semiconductor chip is electrically connected to the external connector via the first connector of the second chip connectors, the second semiconductor, and the conductive connection structure.

6. The semiconductor package of claim 5 ,
wherein the dielectric layer extends to cover the first surface of the embedding substrate; and
wherein the dielectric layer fills the connection window to expose the second surface of the embedding substrate.

7. The semiconductor package of claim 5 , further comprising an adhesive layer fixing the first semiconductor chip to the bottom portion of the cavity.

8. The semiconductor package of claim 5 , wherein the connection window is a single trench or a single hole penetrating a central portion of the bottom portion of the cavity.

9. The semiconductor package of claim 5 , wherein a vertical height of the first chip connectors is greater than a vertical height of the second chip connectors.

10. The semiconductor package of claim 5 ,
wherein the first and second connectors of the first chip connectors each have a vertical length,
wherein the vertical length of the first connector of the first chip connector is greater than a thickness of the bottom portion of the cavity that the connection window penetrates, and
wherein the vertical length of the second connector of the first chip connector is greater than the thickness of the bottom portion of the cavity that the connection window penetrates.

11. The semiconductor package of claim 10 , wherein the first and second connectors of the first chip connectors are bumps.

12. The semiconductor package of claim 5 , wherein the connection window includes a pair of trenches respectively penetrating both edges of the bottom portion of the cavity.

13. The semiconductor package of claim 12 ,
wherein the first connector of the first chip connectors of the first semiconductor chip penetrates one of the trenches from the pair of trenches, and
wherein the second connector of the first chip connectors of the first semiconductor chip penetrates another one of the trenches from the pair of trenches.

14. The semiconductor package of claim 5 , further comprising a third semiconductor chip disposed on the second surface of the embedding substrate and coupled to a first connector of third chip connectors, the first connector of the third chip connectors of the third semiconductor chip connected to the second connector of the first chip connectors,
wherein the second and third semiconductor chips are located side by side without vertically overlapping with each other.

15. The semiconductor package of claim 14 , further comprising a protection layer disposed on the second surface of the embedding substrate to substantially cover the second and third semiconductor chips.

16. The semiconductor package of claim 15 , wherein the protection layer includes an epoxy molding compound (EMC) material.

17. The semiconductor package of claim 5 , wherein the conductive connection structure includes:
a first internal connector disposed on the second surface of the embedding substrate and connected to the second connector of the second chip connectors of the second semiconductor chip;
a first via portion penetrating the embedding substrate and connected to the first internal connector;
a second via portion penetrating the dielectric layer on the first surface of the embedding substrate and connected to the first via portion; and
a second internal connector disposed on the dielectric layer connecting the second via portion to the external connector.

18. The semiconductor package of claim 17 , wherein the conductive connection structure further includes:
a first trace pattern disposed on the first surface of the embedding substrate connecting the first via portion to the second via portion; and
a second trace pattern disposed on the dielectric layer.

19. The semiconductor package of claim 17 ,
wherein the end portions of the first and second connectors of the first chip connectors protrude from a surface of the dielectric layer opposite to the first semiconductor chip; and
wherein a height of the protruded end portions of the first and second connectors of the first chip connectors is substantially equal to a height of the first internal connector.

Assignees

• Sk Hynix Inc

Inventors

• Sung Ki Jun
• Yoo Young Geun

Classifications

• H10W74/117 Primary

  the substrate having spherical bumps for external connection · CPC title

• H10W70/614 Primary

  the multiple chips being integrally enclosed · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title