Structures incorporating and methods of forming metal lines including carbon

Patent metadata

Field	Value
Publication number	US-9634245-B2
Application number	US-201514594038-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Jan 9, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

First claim

What is claimed is:

1. A memory device, comprising:
a lower conductive line extending in a first direction, the lower conductive line comprising alternating layers of at least a first material and at least a second material;
an upper conductive line extending in a second direction and crossing the lower conductive line, the upper conductive line comprising alternating layers of at least a third material and at least a fourth material;
wherein at least one of the alternating layers of the upper and lower conductive lines comprises tungsten and carbon; and
a memory cell stack interposed at an intersection between the upper and lower conductive lines, the memory cell stack including:
a first active element disposed over the lower conductive line and a second active element disposed over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element;
an electrode interposed between the first active element and the lower conductive line; and
a second electrode interposed between the second active element and the upper conductive line.

2. The memory device of claim 1 , wherein the memory device is a phase change memory device, and wherein the first active element is a storage element comprising a first chalcogenide composition and the second active element is a selector element comprising a second chalcogenide composition.

3. The memory device of claim 1 , wherein the at least one of the upper and lower conductive lines is at least partially amorphous.

4. The memory device of claim 1 , wherein the at least one of the upper and lower conductive lines comprises between about 0.5% and about 20% of carbon by atomic percentage.

5. The memory device of claim 1 , wherein the at least one of the upper and lower conductive lines has a surface roughness having a root mean square value less than about 2.5% of a thickness of the at least one of upper and lower conductive lines.

6. The memory device of claim 5 , wherein the thickness of the at least one of the upper and lower conductive lines is less than or equal to about 100 nm, and wherein a width of the at least one of the upper and lower conductive lines is less than or equal to about 50 nm.

7. The memory device of claim 1 , wherein the at least one alloy line is at least partially amorphous.

8. The method of claim 1 , wherein at least two of the first material, the second material, the third material, and the fourth material are a same material.

9. A memory device, comprising:
a lower conductive line extending in a first direction, the lower conductive line comprising alternating layers of at least a first material and at least a second material;
an upper conductive line extending in a second direction and crossing the lower conductive line, the upper conductive line comprising alternating layers of at least a third material and at least a fourth material; and
a phase change memory cell formed at an intersection between the upper and lower conductive lines, the phase change memory cell including an active element comprising a chalcogenide material,
wherein at least one of the first material, the second material, the third material, or the fourth material comprises a metallic conductive line; and
wherein at least one of the first material, the second material, the third material, or the fourth material comprises a conductive carbon containing line, and wherein the conductive carbon containing line has an electrical resistivity in a direction of line extension that is lower than an electrical resistivity of amorphous carbon.

10. The memory device of claim 9 , wherein the layer comprising the conductive carbon containing line comprises multiple layers of graphene.

11. The memory device of claim 10 , wherein the layer comprising the conductive carbon containing line comprises less than 20 monolayers of graphene.

12. The memory device of claim 10 , wherein the layer comprising the conductive carbon containing line has a thickness between about 1 nm and about 10 nm, and wherein a width of the at least one of the upper and lower conductive lines is less than or equal to about 50 nm.

13. The memory device of claim 9 , wherein the layer comprising the metallic conductive line comprises tungsten.

14. The memory device of claim 9 , wherein thicknesses of the carbon containing lines are between about 0.5 nm and about 3 nm, and wherein a width of the at least one of the upper and lower conductive lines is less than or equal to about 50 nm.

15. The memory device of claim 9 , wherein an aspect ratio of the at least one of upper and lower conductive lines is less than about one.

16. The memory device of claim 9 , wherein the phase change memory cell comprises an electrode contacting the at least one of the upper and lower conductive lines.

17. A memory device, comprising:
a lower conductive line extending in a first direction;
an upper conductive line extending in a second direction and crossing the lower conductive line; and
a variable resistance memory cell formed at an intersection between the upper and lower conductive lines,
wherein at least one of the upper and lower conductive lines comprises:
grains comprising at least one of alpha or beta phase tungsten; and
a matrix having a carbon content greater than a carbon content of the grains.

18. The memory device of claim 17 , wherein the at least one of the upper and lower conductive lines is at least partially amorphous.

19. The memory device of claim 17 wherein the matrix is at least partially amorphous.

Assignees

• Micron Technology Inc

Inventors

• Gotti Andrea
• Gealy F Daniel
• Tortorelli Innocenzo
• Varesi Enrico

Classifications

• H01L27/2463

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• H01L45/1666

  Electricity · mapped topic

• H01L45/141

  Electricity · mapped topic