Thermal-disturb mitigation in dual-deck cross-point memories

Patent metadata

Field	Value
Publication number	US-9231202-B2
Application number	US-201313921672-A
Country	US
Kind code	B2
Filing date	Jun 19, 2013
Priority date	Jun 19, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.

First claim

The invention claimed is:

1. A cross-point memory device, comprising:
a first deck comprising a first array of phase-change memory cells, a first word line layer, and a first bit line layer, wherein the first array of phase-change memory cells is disposed between the first word line layer and the first bit line layer;
a second deck comprising a second array of phase-change memory cells, a second word line layer, and a second bit line layer, wherein the second array of phase-change memory cells is disposed between the second word line layer and the second bit line layer; and
a thermal insulation layer disposed between the first bit line layer and the second bit line layer, the thermal insulation layer being in direct contact with the first bit line layer and the second bit line layer.

2. The cross-point memory device according to claim 1 , wherein the thermal insulation layer comprises carbon.

3. The cross-point memory device according to claim 1 , wherein a thermal resistance of a thermal path between the first and second deck is greater than a thermal resistance of a thermal path between memory cells in the same deck.

4. The cross-point memory device according to claim 3 , wherein the thermal insulation layer comprises carbon or a disordered metal alloy.

5. The cross-point memory device according to claim 1 , wherein the phase-change memory cells are formed from a chalcogenide material.

6. The cross-point memory device according to claim 1 , wherein the thermal insulation layer is separated from an electrode of the first deck by the first bit line layer, and is separated from an electrode of the second deck by the second bit line layer.

7. The cross-point memory device according to claim 1 , wherein the cross-point memory device comprises part of part of a solid-state memory array or a solid-state drive.

8. A phase-change memory device, comprising:
a first deck comprising a first array of phase-change memory cells, a first word line layer, and a first bit line layer, wherein the first array of phase-change memory cells is disposed between the first word line layer and the first bit line layer, the phase-change memory cells of the first array being formed from a chalcogenide material;
a second deck comprising a second array of phase-change memory cells, a second word line layer, and a second bit line layer, wherein the second array of phase-change memory cells is disposed between the second word line layer and the second bit line layer, the phase-change memory cells of the second array being formed from a chalcogenide material; and
a thermal insulation layer disposed between the first bit line layer and the second bit line layer, the thermal insulation layer being in direct contact with the first bit line layer and the second bit line layer.

9. The phase-change memory device according to claim 8 , wherein the thermal insulation layer comprises carbon or a disordered metal alloy.

10. The phase-change memory device according to claim 8 , wherein a thermal resistance of a thermal path between the first and second arrays is greater than a thermal resistance of a thermal path between memory cells in the same array.

11. The phase-change memory device according to claim 10 , wherein the thermal insulation layer comprises carbon.

12. The phase-change memory device according to claim 8 , wherein the thermal insulation layer is separated from an electrode of the first array by the first bit line layer, and is separated from an electrode of the second array by the second bit line layer.

13. The phase-change memory device according to claim 8 , wherein the phase-change memory device comprises part of part of a solid-state memory array or a solid-state drive.

14. A method to form a cross-point memory device, the method comprising:
forming first deck comprising a first array of phase-change memory cells, a first word line layer, and a first bit line layer, wherein the first array of phase-change memory cells is disposed between the first word line layer and the first bit line layer;
forming a second deck comprising second array of phase-change memory cells on the first bit line layer, a second word line layer, and a second bit line layer, wherein the second array of phase-change memory cells is disposed between the second word line layer and the second bit line layer; and
forming a thermal insulation layer disposed between the first bit line layer and the second bit line layer, the thermal insulation layer being in direct contact with the first bit line layer and the second bit line layer.

15. The method according to claim 14 , further comprising patterning the first bit line layer before forming the thermal insulation layer, and
patterning the second bit line layer before forming the second array of phase-change memory cells.

16. The method according to claim 14 , wherein the thermal insulation layer comprises carbon or a disordered metal alloy.

17. The method according to claim 14 , wherein a thermal resistance of a thermal path between the first and second arrays is greater than a thermal resistance of a thermal path between memory cells in the same array.

18. The method according to claim 14 , wherein the phase-change memory cells are formed from a chalcogenide material.

19. The method according to claim 14 , wherein the thermal insulation layer is separated from an electrode of the first array by the first bit line layer, and is separated from an electrode of the second array by the second bit line layer.

20. The method according to claim 14 , wherein the cross-point memory device comprises part of part of a solid-state memory array or a solid-state drive.

21. A cross-point memory device, comprising:
a first deck comprising a first word line layer, a first bit line layer, and a first array of memory cells disposed between the first word line layer and the first bit line layer;
a second deck comprising a second word line layer, a second bit line layer, and a second array of memory cells disposed between the second word line layer and the second bit line layer; and
a thermal insulation layer disposed between the first bit line layer and the second bit line layer, the thermal insulation layer being in direct contact with the first bit line layer and the second bit line layer;
wherein the thermal insulation layer comprises tungsten diselenide.

22. The cross-point memory device according to claim 21 , wherein the memory cells are formed from a chalcogenide material.

23. The cross-point memory device according to claim 21 , wherein the thermal insulation layer is not an electrode.

24. The cross-point memory device according to claim 21 , wherein the cross-point memory device comprises part of part of a solid-state memory array or a solid-state drive.

Assignees

• Intel Corp

Inventors

• Pangal Kiran
• Hineman Max F

Classifications

• H01L45/1293 Primary

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic