Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width

Patent metadata

Field	Value
Publication number	US-8936972-B2
Application number	US-201213596234-A
Country	US
Kind code	B2
Filing date	Aug 28, 2012
Priority date	Aug 1, 2012
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.

First claim

What is claimed is:

1. A method of fabricating a field effect transistor (FET) device, comprising the steps of:
providing a semiconductor-on-insulator (SOI) wafer having an SOI layer over a buried oxide (BOX), wherein the SOI layer is present between a buried nitride layer beneath the SOI layer and a nitride cap above the SOI layer;
etching the SOI layer, the buried nitride layer and the nitride cap to form nanowire cores and pads in the SOI layer, wherein the pads are attached at opposite ends of the nanowire cores in a ladder-like configuration, wherein the buried nitride layer is present beneath each of the nanowire cores and the nitride cap is present on top of each of the nanowire cores, and wherein sidewalls of the nanowire cores are exposed;
suspending the nanowire cores over the BOX;
forming epitaxial sidewalls over the sidewalls of the nanowires cores;
removing the buried nitride layer and the nitride cap from the nanowire cores; and
forming a gate stack that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls, wherein the portions of the nanowire cores and the epitaxial sidewalls surrounded by the gate stack serve as channels of the device, wherein the pads and portions of the nanowire cores and the epitaxial sidewalls that extend out from the gate stack serve as source and drain regions of the device.

2. The method of claim 1 , wherein the channels of the device have a pitch of from about 5 nm to about 50 nm.

3. The method of claim 1 , wherein the channels of the device have a pitch of from about 20 nm to about 40 nm.

4. The method of claim 1 , further comprising the step of:
thinning the nanowire cores.

5. The method of claim 1 , wherein the SOI layer comprises a semiconducting material selected from the group consisting of: silicon, silicon germanium and silicon carbon.

6. The method of claim 1 , wherein the nanowire cores are doped with either an n-type dopant or a p-type dopant.

7. The method of claim 1 , wherein the nanowire cores are undoped.

8. The method of claim 4 , wherein the step of thinning the nanowire cores comprises the steps of:
oxidizing the nanowire cores to form an oxide on the nanowire cores;
etching the oxide formed on the nanowire cores; and
repeating the oxidizing and etching steps until a desired nanowire dimension is achieved.

9. The method of claim 1 , wherein the epitaxial sidewalls are doped with either an n-type dopant or a p-type dopant.

10. The method of claim 1 , wherein the epitaxial sidewalls are undoped.

11. The method of claim 1 , wherein the epitaxial sidewalls comprise epitaxial silicon, silicon germanium or silicon carbon.

12. The method of claim 1 , wherein the step of forming the gate stack comprises the steps of:
depositing a conformal gate dielectric film around the nanowire cores and the epitaxial sidewalls;
depositing a conformal metal gate film over the conformal gate dielectric film;
depositing polysilicon over the conformal metal gate film; and
patterning the polysilicon, the conformal gate dielectric film and the conformal metal gate film using a hardmask to form the gate stack.

13. The method of claim 12 , wherein the conformal gate dielectric film is selected from the group consisting of: silicon dioxide, silicon oxynitride, hafnium oxide and hafnium silicate.

14. The method of claim 12 , wherein the conformal metal gate film is selected from the group consisting of: tantalum nitride and titanium nitride.

15. The method of claim 1 , wherein the buried nitride layer and the nitride cap are removed from the nanowire cores using a phosphoric acid etch.

16. A FET device, comprising:
a wafer having a buried oxide (BOX);
nanowire cores and pads attached at opposite ends of the nanowire cores in a ladder-like configuration on the BOX, wherein the nanowire cores are suspended over the BOX, and wherein the nanowire cores each have two flat opposing sidewalls;
epitaxial sidewall covering only the two flat opposing sidewalls of the nanowire cores and which extend along each of the nanowire cores in a plane parallel to the BOX; and
a gate stack that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls, wherein the portions of the nanowire cores and the epitaxial sidewalls surrounded by the gate stack serve as channels of the device, wherein the pads and portions of the nanowire cores and the epitaxial sidewalls that extend out from the gate stack serve as source and drain regions of the device.

17. The FET device of claim 16 , wherein the nanowire cores are doped with either an n-type dopant or a p-type dopant.

18. The FET device of claim 16 , wherein the nanowire cores are undoped.

19. The FET device of claim 16 , wherein the epitaxial sidewalls are doped with either an n-type dopant or a p-type dopant.

20. The FET device of claim 16 , wherein the epitaxial sidewalls are undoped.

21. The FET device of claim 16 , wherein the channels of the device have a pitch of from about 5 nm to about 50 nm.

22. The FET device of claim 16 , wherein the channels of the device have a pitch of from about 20 nm to about 40 nm.

Assignees

• Bangsaruntip Sarunya
• Cohen Guy
• Lin Chung-Hsun
• Sleight Jeffrey W
• IBM

Inventors

• Bangsaruntip Sarunya
• Cohen Guy
• Lin Chung-Hsun
• Sleight Jeffrey W

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2924

  Structures · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title