Semiconductor package including a semiconductor die having redistributed pads

US9633951B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9633951-B2
Application numberUS-59520606-A
CountryUS
Kind codeB2
Filing dateNov 10, 2006
Priority dateNov 10, 2005
Publication dateApr 25, 2017
Grant dateApr 25, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor package, comprising: a semiconductor die including a power device, said semiconductor die having a plurality of electrodes disposed on one major surface thereof, each of said plurality of electrodes having a respective first area; an insulation body disposed around said semiconductor die; and at least three of conforming conductive pads each providing an external connection for a respective one of said plurality of electrodes; said at least three of conforming conductive pads extending at least partially over said semiconductor die, and extending over and conforming to respective portions of said insulation body; each of said at least three of conforming conductive pads directly and physically coupled to the respective one of said plurality of electrodes, and having an area that is larger than said respective first area of said respective one of said plurality of electrodes to which it is coupled. 2. The package of claim 1 , wherein each of said at least three of conforming conductive pads includes a solderable surface. 3. The package of claim 1 , further comprising a passivation body disposed over said semiconductor die, said passivation body including an opening over each of said at least three of conforming conductive pads. 4. The package of claim 3 , wherein said passivation body includes solder resist characteristics. 5. The package of claim 1 , further comprising a conductive clip having a web portion coupled to another major surface of said semiconductor die opposite said one major surface. 6. The package of claim 5 , wherein said conductive clip includes at least one lead adjoining said web portion and including a connection surface generally coplanar with a top surface of said at least three of conforming conductive pads. 7. The package of claim 6 , wherein said web portion is coupled to said another major surface by a conductive adhesive body. 8. The package of claim 7 , wherein said conductive adhesive body is comprised of solder or a conductive epoxy. 9. The package of claim 1 , wherein said semiconductor die is a III-nitride semiconductor device. 10. The package of claim 1 , further comprising a conductive clip coupled to another major surface of said semiconductor die opposite said one major surface. 11. The package of claim 10 , wherein said conductive clip is coupled to said another major surface with a conductive adhesive body. 12. The package of claim 11 , wherein said conductive adhesive body is comprised of solder or a conductive epoxy. 13. The package of claim 10 , wherein said conductive clip includes at least one lead and a web portion, wherein said at least one lead extending from an edge of said web portion and including a connection surface generally coplanar with a top surface of said at least three of conforming conductive pads. 14. The package of claim 13 , wherein said web portion of said conductive clip is coupled to said another major surface with a conductive adhesive body. 15. The package of claim 14 , wherein said conductive adhesive body is comprised of solder or a conductive epoxy.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • changes in dispositions · CPC title

  • Soldering or alloying · CPC title

  • by plating, e.g. electroless plating or electroplating · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

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Frequently asked questions

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What does patent US9633951B2 cover?
A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
Who is the assignee on this patent?
Pavier Mark, Sawle Andrew N, Standing Martin, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10W74/117. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).