Hybrid pitch package with ultra high density interconnect capability

Patent metadata

Field	Value
Publication number	US-9633938-B2
Application number	US-201514866491-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

First claim

The invention claimed is:

1. A method of forming a hybrid pitch package comprising:
obtaining a package having only standard package pitch sized features in a standard package pitch zone of the package and in a smaller processor pitch sized zone of the package; then
forming a protective mask over the standard package pitch zone of the package that is adjacent to the smaller processor pitch sized zone of the package; and then
forming smaller processor pitch sized features in the smaller processor pitch sized zone, wherein the smaller processor pitch sized features have a pitch at least three times smaller than that of the standard package pitch sized features.

2. The method of claim 1 , wherein the smaller processor pitch sized features have a bump pitch of between 10 and 50 micrometers and the standard package pitch sized features have a bump pitch of between 100 micrometers and 200 micrometers.

3. The method of claim 1 , wherein the standard package pitch sized features include conductive package upper contacts formed on conductive via contacts which are formed on conductive lower contacts, and wherein forming smaller processor pitch sized features includes removing all or a portion of a height of at least one upper contact from over at least one conductive via contact in the smaller processor pitch sized zone.

4. The method of claim 1 , wherein the standard package pitch sized features are formed according to standard package POR and include conductive upper contacts having a height of at least 10 micrometers; and wherein forming smaller processor pitch sized features includes forming features according to a chip POR and having a height of less than 10 micrometers.

5. The method of claim 4 , wherein forming smaller processor pitch sized features includes forming dielectric layers having a thickness of between 0.1 and 0.3 micrometers, and conductive material layers having a thickness of between 1 and 3 micrometers; and wherein the dielectric layers are formed by atomic layer deposition (ALD) and wherein the conductive material layers are formed by chemical vapor deposition (CVD).

6. The method of claim 1 , wherein the standard package zone has only standard package pitch sized features, and the reduced pitch size zone has reduced pitch sized features formed over standard package pitch sized features.

7. The method of claim 1 , wherein obtaining the package includes receiving the obtaining a package substrate from a location that is different than the location where forming occurs.

8. The method of claim 1 , wherein forming smaller processor pitch sized features includes:
removing a first upper contact from over a conductive via contact that is below the upper contact;
forming alternating layers of only dielectric material and only conductive material over the conductive via using a chip POR and having a reduced pitch;
wherein the alternating layers of dielectric material have a thickness of between 0.1 and 0.3 micrometers, and the alternating layers of conductive material have a thickness of between 1 and 3 micrometers; and
wherein the dielectric layers are formed by atomic layer deposition (ALD) and the conductive material layers are formed by chemical vapor deposition (CVD).

9. The method of claim 1 , wherein forming smaller processor pitch sized features includes:
removing a first upper contact from over a conductive via contact that is below the upper contact;
forming patterned layers of combined dielectric material and conductive material over the conductive via using a chip POR and having a reduced pitch;
wherein the patterned layers have a thickness of between 1 and 3 micrometers; and
wherein the patterned layers include one of conductive upper contacts, conductive traces, or layers that form capacitors.

10. A hybrid pitch package comprising:
a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone of the package;
the standard package pitch zone having only standard package pitch sized features; and
the smaller processor pitch sized zone having smaller processor pitch sized features formed over standard package pitch sized features, wherein the smaller processor pitch sized features have a pitch at least three times smaller than that of the standard package pitch sized features.

11. The package of claim 10 , wherein the smaller processor pitch sized features have a bump pitch of between 10 and 50 micrometers and the standard package pitch sized features have a bump pitch of between 100 micrometers and 200 micrometers.

12. The package of claim 10 , wherein the smaller processor pitch sized features are formed on a conductive via or a portion of a height of at least one upper contact having a standard package pitch size.

13. The package of claim 10 , wherein the standard package pitch sized features include conductive upper contacts having a height of at least 10 micrometers; and wherein the smaller processor pitch sized features have a height of less than 10 micrometers.

14. The package of claim 13 , wherein the smaller processor pitch sized features include dielectric layers having a thickness of between 0.1 and 0.3 micrometers, and conductive material layers having a thickness of between 1 and 3 micrometers.

15. The package of claim 10 , wherein the standard package zone has only standard package pitch sized features, and the reduced pitch size zone has reduced pitch sized features formed over standard package pitch sized features.

16. The package of claim 10 , wherein the smaller processor pitch sized features include:
alternating layers of only dielectric material and only conductive material having a reduced bump pitch over a conductive via having a standard package bump pitch; and
wherein the alternating layers of dielectric material have a thickness of between 0.1 and 0.3 micrometers, and the alternating layers of conductive material have a thickness of between 1 and 3 micrometers.

17. The package of claim 10 , wherein the smaller processor pitch sized features include:
patterned layers of combined dielectric material and conductive material having a reduced bump pitch over a conductive via having a standard package bump pitch;
wherein the patterned layers have a thickness of between 1 and 3 micrometers; and
wherein the patterned layers include one of conductive upper contacts; conductive traces, or layers that form capacitors.

18. A system for computing comprising:
an integrated chip mounted on a hybrid pitch package, the hybrid pitch package including:
a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone of the package;
the standard package pitch zone having only standard package pitch sized features; and
the smaller processor pitch sized zone having smaller processor pitch sized features formed over standard package pitch sized features, wherein the smaller processor pitch sized features have a pitch at least three times smaller than that of the standard package pitch sized features.

19. The system of claim 18 , wherein the smaller processor pitch sized features have a bump pitch of between 10 and 50 micrometers and the standard package pitch sized features have a bump pitch of between 100 micrometers and 200 micrometers.

20. The method of claim 1 , wherein the smaller processor pitch sized features and the standard package pitch sized features are surface contacts upon which solder balls can be formed.

21. The package of claim 10 , wherein the smaller processor

Assignees

• Intel Corp

Inventors

• Manusharow Mathew J
• Sobieski Daniel N
• Roy Mihir K
• Lambert William J

Classifications

• H10P14/6328

  Deposition from the gas or vapour phase · CPC title

• H10P14/61

  using masks · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title