Apparatus and method for fast phase locking for digital phase locked loop

Patent metadata

Field	Value
Publication number	US-9628094-B2
Application number	US-201314127963-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Sep 26, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

First claim

We claim:

1. An integrated circuit (IC) comprising:
a node to provide a reference clock;
a digitally controlled oscillator (DCO) to generate an output clock;
a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock;
control logic operable to reset or disable the DCO and the divider, and operable to release reset in synchronization with the reference clock; and
a clock distribution network to receive output clock of the DCO, wherein the divider is operable to divide a clock received from the clock distribution network.

2. The IC of claim 1 , wherein the DCO comprises a plurality of DCO cells and switches, wherein each of the switches is coupled to an output of a DCO cell of the plurality of DCO cells, and wherein each of the switches is operable to couple the output of the DCO cell to a known voltage level.

3. The IC of claim 1 , wherein the DCO is operable to oscillate when reset is released.

4. The IC of claim 2 , wherein the control logic is operable to control the switches.

5. The IC of claim 1 , wherein the divider is operable to divide the output clock in synchronization with the reference clock when the control logic releases reset.

6. The IC of claim 1 , wherein the control logic is operable to reset only the divider when delay of the clock distribution network is substantially greater than one cycle of the output clock.

7. The IC of claim 1 , wherein the control logic is operable to reset the divider and the DCO when delay of the clock distribution network is less than one cycle of the output clock.

8. An integrated circuit (IC) comprising:
a node to provide a reference clock;
a digitally controlled oscillator (DCO) to generate an output clock;
a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock;
control logic operable to reset or disable the DCO and the divider, and operable to release reset in synchronization with the reference clock; and
a digital loop filter (DLF) coupled to provide a digital control word to the DCO.

9. The IC of claim 8 , wherein the control logic is operable to adjust filter coefficients of the DLF when the control logic is to reset the divider.

10. The IC of claim 8 , wherein the DCO comprises a plurality of DCO cells and switches, wherein each of the switches is coupled to an output of a DCO cell of the plurality of DCO cells, and wherein each of the switches is operable to couple the output of the DCO cell to a known voltage level.

11. The IC of claim 8 , wherein the DCO is operable to oscillate when reset is released.

12. The IC of claim 10 , wherein the control logic is operable to control the switches.

13. The IC of claim 8 , wherein the divider is operable to divide the output clock in synchronization with the reference clock when the control logic releases reset.

14. A system comprising:
a memory;
an integrated circuit coupled to the memory, the integrated circuit comprising:
a node to provide a reference clock;
a digitally controlled oscillator (DCO) to generate an output clock;
a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock;
control logic operable to reset or disable the DCO and the divider, and operable to release reset in synchronization with the reference clock; and
a clock distribution network to receive output clock of the DCO, wherein the divider is operable to divide a clock received from the clock distribution network; and

a wireless interface for allowing the integrated circuit to communicate with another device.

15. The system of claim 14 , wherein the integrated circuit forms part of a digital phase locked loop (DPLL).

16. The system of claim 14 further comprises a display unit.

Assignees

• Intel Corp

Inventors

• Lotfy Amr M
• Abdelsalam Mohamed A
• Abd El-Mejeed Mamdouh O
• Kurd Nasser A
• Abdelmoneum Mohamed A
• Elzinga Mark
• Park Young Min
• Rapeta Jagannadha R
• Musunuri Surya

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/103

  the additional signal being a digital signal · CPC title

• H03L7/105 Primary

  Resetting the controlled oscillator when its frequency is outside a predetermined limit · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/10

  for assuring initial synchronisation or for broadening the capture range · CPC title