Phase locked loop circuits

Patent metadata

Field	Value
Publication number	US-10003343-B2
Application number	US-201715404059-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Jan 25, 2016
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

First claim

The invention claimed is:

1. A phase locked loop circuit comprising:
an input terminal configured to receive an input signal;
a phase detector configured to compare a phase of the input signal with a phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal, wherein a difference between a property of the up-phase signal and a property of the down-phase-signal, is indicative of a phase difference between the input signal and the feedback signal;
an oscillator-driver configured to apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal, and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal;
a variable-frequency-oscillator configured to provide the feedback signal for the phase detector, wherein the variable-frequency-oscillator is configured to set a frequency of the feedback signal based on the oscillator-driver-output-signal;
a controller configured to set the up-weighting-value and the down-weighting-value as a first-set-of-weighting-values, compare a loop filter voltage to a limit-value, and replace the first-set-of-weighting-values with a second-set-of-weighting-values after the loop filter voltage reaches the limit-value without satisfying a threshold value; and
an output terminal configured to provide a local oscillator signal based on the feedback signal.

2. The phase locked loop circuit of claim 1 , wherein the controller is configured to process an operating signal of the phase locked loop circuit to determine whether or not the input signal is in phase with the feedback signal, and, after the input signal is in phase with the feedback signal, set the up-weighting-value as the same value as the down-weighting-value.

3. The phase locked loop circuit of claim 1 , wherein the oscillator-driver is configured to multiply the up-phase signal by the up-weighting-value in order to provide the weighted-up-phase signal, and multiply the down-phase signal by the down-weighting-value in order to provide the weighted-down-phase signal.

4. The phase locked loop circuit of claim 1 , wherein following a transition in the input signal, the phase detector is configured to compare the phase of the input signal with the phase of the feedback signal in order to provide the up-phase signal and down-phase-signal.

5. The phase locked loop circuit of claim 4 , wherein the phase detector is configured to compare the phase of the input signal with the phase of the feedback signal following only a rising-edge transition or only a falling-edge transition in the input signal.

6. The phase locked loop circuit of claim 1 , wherein the phase detector is configured to provide a pulse in the up-phase-signal in response to a transition in the input signal.

7. The phase locked loop circuit of claim 6 , wherein the phase detector is configured to provide a pulse in the down-phase-signal after the pulse in the up-phase-signal.

8. The phase locked loop circuit of claim 7 , wherein the difference between the duration of the pulse in the up-phase signal and the duration of the pulse in the down-phase-signal, is indicative of a phase difference between the input signal and the feedback signal.

9. The phase locked loop circuit of claim 7 , wherein the duration of one of the pulses in the up-phase signal and the down-phase-signal is indicative of a clock frequency.

10. The phase locked loop circuit of claim 7 , wherein the phase detector is configured to set the duration of the pulse in the up-phase signal as equal to the duration of the pulse in the down-phase-signal when the input signal is in phase with the feedback signal.

11. The phase locked loop circuit of claim 1 , wherein the oscillator-driver is configured to determine an average value of the weighted-up-phase signal and the weighted-down-phase signal in order to provide the oscillator-driver-output-signal.

12. The phase locked loop circuit of claim 1 , wherein the first-set-of-weighting-values defines a first relative relationship between the up-weighting-value and the down-weighting-value, and the second-set-of-weighting-values defines a second, different relative relationship between the up-weighting-value and the down-weighting-value.

13. The phase locked loop circuit of claim 1 , wherein the first-set-of-weighting-values defines a first relative relationship between the up-weighting-value and the down-weighting-value, the second-set-of-weighting-values defines the same relative relationship between the up-weighting-value and the down-weighting-value, and the controller is configured to reset the oscillator-driver-output-signal before replacing the first-set-of-weighting-values with the second-set-of-weighting-values.

14. A radio tuner comprising a clock recovery circuit, wherein the clock recovery circuit includes the phase locked loop circuit of claim 1 .

15. A method of operating a phase locked loop circuit, the phase locked loop comprising a variable-frequency-oscillator, wherein the method comprises:
receiving an input signal;
comparing a phase of the input signal with a phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal, wherein a difference between a property of the up-phase signal and a property of the down-phase-signal is indicative of a phase difference between the input signal and the feedback signal;
applying an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal;
applying a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and
combining the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal;
setting a frequency of a variable-frequency-oscillator based on the oscillator-driver-output-signal, wherein the variable-frequency-oscillator provides the feedback signal;
setting the up-weighting-value and the down-weighting-value as a first-set-of-weighting-values,
comparing a loop filter voltage to a limit-value;
replacing the first-set-of-weighting-values with a second-set-of-weighting-values after the loop filter voltage reaches the limit-value without satisfying a threshold value; and
providing a local oscillator signal based on the feedback signal.

16. The phase locked loop circuit of claim 1 , wherein the controller is configured to process an operating signal of the phase locked loop circuit to determine whether or not the input signal is in phase with the feedback signal, and, after the input signal is not in phase with the feedback signal, set the up-weighting-value as a different value to the down-weighting-value.

Assignees

• Nxp Bv

Inventors

• Kianush Kaveh
• Pol Evert-Jan
• Gevel Marcel Van De

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/089 Primary

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/105

  Resetting the controlled oscillator when its frequency is outside a predetermined limit · CPC title