Assymetric poly gate for optimum termination design in trench power MOSFETs

Patent metadata

Field	Value
Publication number	US-9627526-B2
Application number	US-201414224043-A
Country	US
Kind code	B2
Filing date	Mar 24, 2014
Priority date	Mar 2, 2012
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

First claim

The invention claimed is:

1. A semiconductor device formed on a semiconductor substrate comprising:
an active area including a plurality of transistors each of which has source, body, drain and gate regions; and
a termination area surrounding said active area, said termination area including at least an innermost termination trench adjacent to the active area and an outermost termination trench spaced apart from the innermost termination trench, each having electrically conductive material disposed therein and electrically insulative material disposed between said electrically conductive material and material of said substrate, the innermost termination trench having a gate portion formed by said electrically conductive material having a cross-sectional area of said gate portion smaller than a cross-sectional area of said gate region of the transistor in said active area, said gate portion in superimposition with, and insulated from, a shielding gate region formed of said conductive material at a lower portion of said innermost termination trench adjacent the active area, with said source region and said shielding gate region being electrically connected, with a top surface of said substrate material in the termination area being recessed at least to a bottom of said gate portion and said electrically conductive material disposed in said outermost termination trench spaced-apart from said innermost termination trench being electrically connected to a substrate region within the termination area.

2. The device as recited in claim 1 wherein said gate portion disposed in said innermost termination trench adjacent the active area is insulated from the substrate material by said electrically insulative material having a first thickness between said gate portion and said body region adjacent said gate portion and a second thickness between said gate portion and said substrate material in termination area, said first thickness being less than said second thickness.

3. The device as recited in claim 1 wherein said innermost termination trench adjacent the active area has a width and a depth substantially identical to an active gate trench disposed in the active area.

4. A semiconductor device formed on a semiconductor substrate comprising:
an active area including a plurality of transistors each of which has source, body, drain and gate regions; and
a termination area surrounding said active area, said termination area including an innermost termination trench adjacent to the active area and an outermost termination trench spaced apart from the innermost termination trench, each of said innermost termination trench and said outermost termination trench being filled with electrically conductive material and electrically insulative material, with said electrically insulative material being disposed between said electrically conductive material and material of said substrate, the innermost termination trench having a gate portion formed by said electrically conductive material having a cross-sectional area of said gate portion smaller than a cross-sectional area of said gate region of the transistor in said active area, with the electrically conductive material disposed in said outermost termination trench; and
an electrical contact extending from both the electrically conductive material disposed in said outermost termination trench and said substrate, terminating upon a surface of an electrically insulative layer spaced-apart from said substrate.

5. The device as recited in claim 4 wherein said gate portion is insulated from the substrate material by said electrically insulative material having a first thickness disposed between said gate portion and said body region, and a second thickness located between said gate portion and said substrate material in said termination area, said first thickness less than said second thickness.

6. The device as recited in claim 4 wherein said innermost termination trench adjacent to the active area has a width and a depth substantially identical to an active gate trench disposed in the active area.

7. The device as recited in claim 4 wherein said gate portion in superimposition with and insulated from a shielding gate region formed of said conductive material at a lower portion of said innermost termination trench adjacent to the active area.

8. The device as recited in claim 7 wherein said source region and said shielding gate region are electrically connected.

9. The device as recited in claim 7 wherein said electrically conductive material disposed in said outermost termination trench and said innermost termination trench is the same.

Assignees

• Lee Yeeheng
• Ding Yongping
• Wang Xiaobin
• Alpha & Omega Semiconductor

Inventors

• Lee Yeeheng
• Ding Yongping
• Wang Xiaobin

Classifications

• H01L29/7811 Primary

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/117 Primary

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title