Semiconductor device having work-function metal and method of forming the same

Patent metadata

Field	Value
Publication number	US-9627500-B2
Application number	US-201514972704-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Jan 29, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a memory cell area and a logic area;
a first active area and a second active area in the memory cell area on the substrate;
a third active area in the logic area on the substrate;
an insulating layer on the substrate, the insulating layer configured to cover the first, second and third active areas;
a first gate electrode configured to pass through the insulating layer, cover a side surface of the first active area, and cross the first active area, the first gate electrode including,
a first P-work-function metal layer in the first active area,
a first capping layer on the first P-work-function metal layer,
a first N-work-function metal layer on the first capping layer,
a first barrier metal layer on the first N-work-function metal layer, and
a first conductive layer on the first barrier metal layer, the first conductive layer having a different material from the first barrier metal layer;

a second gate electrode configured to pass through the insulating layer, cover a side surface of the second active area, and cross the second active area, the second gate electrode including,
a second capping layer in the second active area,
a second N-work-function metal layer on the second capping layer,
a second barrier metal layer on the second N-work-function metal layer, and
a second conductive layer on the second barrier metal layer, the second conductive layer having a different material from the second barrier metal layer; and

a third gate electrode configured to pass through the insulating layer, cover a side surface of the third active area, and cross the third active area, the third gate electrode having a width smaller than the first gate electrode and the second gate electrode and not having the first and second conductive layers, the third gate electrode including,
a second P-work-function metal layer in the third active area,
a third capping layer on the second P-work-function metal layer,
a third N-work-function metal layer on the third capping layer, and
a third barrier metal layer on the third N-work-function metal layer.

2. The device of claim 1 , wherein the first N-work-function metal layer, the second N-work-function metal layer, and the third N-work-function metal layer are thicker than the first P-work-function metal layer and the second P-work-function metal layer.

3. The device of claim 1 , wherein the first barrier metal layer, the second barrier metal layer, and the third barrier metal layer are thicker than the first N-work-function metal layer, the second N-work-function metal layer, and the third N-work-function metal layer.

4. The device of claim 1 , wherein the first P-work-function metal layer and the second P-work-function metal layer include titanium nitride (TiN).

5. The device of claim 1 , wherein the first capping layer, the second capping layer, and the third capping layer include TiN.

6. The device of claim 1 , wherein the first N-work-function metal layer, the second N-work-function metal layer, and the third N-work-function metal layer include one of titanium aluminum carbide (TiAlC) and titanium aluminide (TiAl).

7. The device of claim 1 , wherein the first barrier metal layer, the second barrier metal layer, and the third barrier metal layer include TiN.

8. The device of claim 1 , wherein the first conductive layer and the second conductive layer include tungsten (W).

9. The device of claim 1 , further comprising:
a gate dielectric layer between the first active area and the first gate electrode, between the second active area and the second gate electrode, and between the third active area and the third gate electrode,
wherein an upper surface of the gate dielectric layer and an upper surface of the first, second and third gate electrodes are at a same level.

10. The device of claim 9 , wherein the first P-work-function metal layer, the second capping layer, and the second P-work-function metal layer directly contact the gate dielectric layer.

11. The device of claim 1 , wherein the second gate electrode does not have the first P-work-function metal layer and the second P-work-function metal layer.

12. The device of claim 1 , wherein upper surfaces of the insulating layer, the first P-work-function metal layer, the second P-work-function metal layer, the first capping layer, the second capping layer, the third capping layer, the first N-work-function metal layer, the second N-work-function metal layer, the third N-work-function metal layer, the first barrier metal layer, the second barrier metal layer, the third barrier metal layer, the first conductive layer, and the second conductive layer are at a same level.

13. The device of claim 1 , further comprising:
a first source/drain on the first active area, the first source/drain having an upper portion adjacent to an outer sidewall of the first gate electrode, the upper portion having an upper surface at a level higher than a lower surface of the first gate electrode;
a second source/drain on the second active area, the second source/drain having an upper portion adjacent to an outer sidewall of the second gate electrode, the upper portion having an upper surface at a level higher than a lower surface of the second gate electrode, and
a third source/drain on the third active area, the third source/drain having an upper portion adjacent to an outer sidewall of the third gate electrode, the upper portion having an upper surface at a level higher than a lower surface of the third gate electrode,
wherein the upper surface of the upper portion of the second source/drain is at a different level than the upper surface of the upper portion of the first source/drain and the upper surface of the upper portion of the third source/drain.

14. The device of claim 13 , wherein the upper surface of the upper portion of the second source/drain is at a level higher than the upper surface of the upper portion of the first source/drain and the upper surface of the upper portion of the third source/drain.

15. A semiconductor device comprising:
a substrate having a memory cell area and a logic area;
a first active area in the memory cell area on the substrate;
a second active area in the logic area on the substrate;
an insulating layer on the substrate, the insulating layer configured to cover the first and second active areas;
a first gate electrode configured to pass through the insulating layer, cover a side surface of the first active area, and cross the first active area, the first gate electrode including,
a first work-function metal layer in the first active area,
a first barrier metal layer on the first work-function metal layer, and
a conductive layer on the first barrier metal layer, the conductive layer having a different material from the first barrier metal layer,

a second gate electrode configured to pass through the insulating layer, cover a side surface of the second active area, and cross the second active area, the second gate electrode having a width smaller than the first gate electrode and not having the first conductive layer, the second gate electrode including,
a second first work-function metal layer in the second active area, and
a second barrier metal layer on the second first work-function metal layer.

16. A semiconductor device comprising:
a substrate having a memory cell area and a logic area;
a first well in the memory cell area on the substrate;
a second well in the logic area on the substrate;
an insulating layer on the substrate, the insulating layer configured to cover t

Assignees

• Kim Juyoun
• Samsung Electronics Co Ltd

Inventors

• Kim Juyoun

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title