Directional pre-clean in silicide and contact formation

Patent metadata

Field	Value
Publication number	US-9230795-B1
Application number	US-201414527300-A
Country	US
Kind code	B1
Filing date	Oct 29, 2014
Priority date	Oct 29, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

First claim

What is claimed is:

1. A method comprising:
etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening;
performing a bombardment to bombard a surface region of the underlying region through the opening;
after the bombardment, reacting the surface region with a process gas to form a reaction layer; and
performing an anneal to remove the reaction layer.

2. The method of claim 1 , wherein the bombardment is performed vertically.

3. The method of claim 1 , wherein the reacting the surface region is performed at a temperature higher than about 60° C.

4. The method of claim 3 , wherein the temperature is between about 60° C. and about 200° C.

5. The method of claim 1 further comprising, before the bombardment, forming a conformal dielectric layer extending into the opening, wherein the conformal dielectric layer is bombarded in the bombardment.

6. The method of claim 1 , wherein the underlying region comprises a source/drain region of a Metal-Oxide-Semiconductor (MOS) device, and the method further comprises, after the anneal, performing a silicidation to silicide a surface portion of the source/drain region.

7. The method of claim 1 , wherein the underlying region comprises a source/drain silicide region of a Metal-Oxide-Semiconductor (MOS) device, and the method further comprises, after the anneal, forming a contact plug in the opening.

8. The method of claim 1 , wherein the reacting the surface region with the process gas comprises reacting with NF 3 and NH 3 .

9. A method comprising:
etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening;
reacting a surface region of the underlying region with a process gas to form a reaction layer, wherein the reaction layer comprises a first portion at a bottom of the opening and overlying the underlying region, and a second portion on a top surface of the dielectric layer, with substantially no reaction layer formed on sidewalls of the opening; and
performing an anneal to remove the reaction layer.

10. The method of claim 9 further comprising, before the reacting the surface region, performing a bombardment to bombard the surface region and a top surface region of the dielectric layer.

11. The method of claim 10 further comprising, before the bombardment, forming a conformal dielectric layer extending into the opening.

12. The method of claim 10 , wherein the bombardment is performed vertically.

13. The method of claim 9 , wherein the reacting the surface region is performed at a temperature higher than about 60° C.

14. The method of claim 9 , wherein the underlying region comprises a source/drain region of a Metal-Oxide-Semiconductor (MOS) device, and the method further comprises, after the anneal, performing a silicidation to silicide a surface portion of the source/drain region.

15. The method of claim 9 , wherein the reacting the surface region with the process gas comprises reacting the surface region with NF 3 and NH 3 .

16. A method comprising:
etching an Inter-Layer Dielectric (ILD) to expose a source/drain region of a Metal-Oxide-Semiconductor (MOS) device;
performing a first vertical bombardment to bombard a first surface layer of the source/drain region;
performing a first reaction to react the first surface layer with a first process gas comprising NF 3 and NH 3 , wherein a first reaction layer is generated on a surface of the source/drain region;
performing a first anneal to decompose the first reaction layer; and
forming a silicide region over the source/drain region.

17. The method of claim 16 , wherein the first reaction is performed at a temperature higher than about 60° C.

18. The method of claim 16 further comprising, after the silicide region is formed:
performing a second vertical bombardment to bombard a second surface layer of the silicide region;
performing a second reaction to react the second surface layer with a second process gas comprising NF 3 and NH 3 , wherein a second reaction layer is generated on a surface of the silicide region; and
performing a second anneal to decompose the second reaction layer.

19. The method of claim 16 further comprising, after the etching the ILD and before the first vertical bombardment, forming an oxide layer using a conformal deposition method, wherein the oxide layer extends into an opening formed in the etching the ILD.

20. The method of claim 16 , wherein the first vertical bombardment is performed using a process gas selected from the group consisting of argon, helium, nitrogen (N 2 ), hydrogen (H 2 ), xenon, arsenic, germanium, phosphorous, and combinations thereof.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wang Yu-Shiuan
• Hsu Hung-Chang
• Chu Li-Wei
• Lin Sheng-Hsuan
• Huang Chun-Hsien
• Lin Yu-Hung
• Chang Chih-Wei
• Lin Wei-Jung

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P50/642

  Chemical etching · CPC title