Dual work function buried gate type transistor and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9240453-B2
Application number	US-201414327197-A
Country	US
Kind code	B2
Filing date	Jul 9, 2014
Priority date	Jan 29, 2014
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.

First claim

What is claimed is:

1. A transistor comprising:
a substrate having an active region defined by an isolation layer;
a first trench defined in the active region and a second trench defined in the isolation layer;
a fin region formed under the first trench; and
a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches,
wherein the buried gate electrode includes:
a first work function layer formed on the sidewalls of the fin region;
a second work function layer formed on sidewalls of the first trench and the second trench;
a third work function layer positioned over the fin region and contacting the second work function layer; and
a low resistance layer contacting the third work function layer and partially filling the first and second trenches.

2. The transistor according to claim 1 , wherein the third work function layer has a work function higher than the first work function layer and the second work function layer.

3. The transistor according to claim 1 , wherein the third work function layer includes a high work function material, and the first work function layer and the second work function layer include a low work function material.

4. The transistor according to claim 1 , wherein the first work function layer and the second work function layer include an N-type polysilicon layer.

5. The transistor according to claim 1 , wherein the low resistance layer includes a metal-containing material which has a specific resistance lower than the first work function layer and the second work function layer.

6. The transistor according to claim 1 , wherein the third work function layer includes a metal nitride, and the low resistance layer includes a low resistance metal-containing layer.

7. The transistor according to claim 1 , wherein the second work function layer, the third work function layer and the low resistance layer are positioned at a level lower than a top surface of the substrate.

8. The transistor according to claim 1 , further comprising:
a gate dielectric layer between the second work function layer and the first and second trenches.

9. The transistor according to claim 1 , further comprising:
a first impurity region and a second impurity region separated by the first trench and formed in the substrate.

10. The transistor according to claim 9 , wherein the first and second impurity regions have a depth to overlap with the second work function layer.

Assignees

• Sk Hynix Inc

Inventors

• Oh Tae-Kyung

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title